| 2025 | DEFA: Design Space Exploration for FPGA Overlay Accelerators Through Frequency Prediction and Bayesian Optimization. | Qilong Zhu, Yunfei Dai, Shiyan Bi, Huizhen Kuang, Dylan Wang, Wenbo Yin, Lingli Wang |
| 2025 | Routing Struggle: A Metric to Quantify Routability. | Sadegh Yazdanshenas, Jeffrey Chromczak |
| 2025 | ReconFormer: A Multi-Level Run-Time Reconfigurable System-on-Chip for Accelerating Transformers. | Je Yang, Gabriele Tombesi, Joseph Zuckerman, Luca P. Carloni |
| 2025 | FAME: FPGA Acceleration of Secure Matrix Multiplication with Homomorphic Encryption. | Zhihan Xu, Rajgopal Kannan, Viktor K. Prasanna |
| 2025 | A High-Performance and Resource-Efficient FPGA-Based Multi-Object Tracking System Using Event Cameras. | Wei Xiong, Jianfan Zhang, Xingzhe Zhu, Jiacheng Cao, Jian Wang, Jinmei Lai |
| 2025 | Refining Datapath for Microscaling ViTs. | Can Xiao, Jianyi Cheng, Yiren Zhao |
| 2025 | Live Demonstration: Continuous Processing of Event-Data with Graph Convolutional Neural Networks Implemented for SoC FPGA. | Piotr Wzorek, Kamil Jeziorek, Marcin Kowalczyk, Krzysztof Blachut, Tomasz Kryjak, Marek Gorgon |
| 2025 | Aspo: Constraint-Aware Bayesian Optimization for Fpga-Based Soft Processors. | Haoran Wu, Ce Guo, Wayne Luk, Robert Mullins |
| 2025 | AffiNiTy: A Multi-Scalar Multiplication Accelerator with a Novel Batched Inversion Architecture. | Tong Wu, Niall Emmart, Oliver Diessel |
| 2025 | ATAPP: Architecture and Technology Aware Power Predictor for Unseen FPGAS. | Zhigang Wei, Aman Arora, Emily Shriver, Lizy K. John |
| 2025 | Identifying Sat Resilient Blocks Through LUT Switching Analysis for Breaking Compound Logic Locking Schemes. | Binbin Wang, Xinmu Wang, Xinyu Zhang, Shibo Tang, Huisi Zhou, Wei Hu |
| 2025 | Interconnection-Aware Resynthesis for Improving FPGA Physical Design. | Xiaoke Wang, Dirk Stroobandt |
| 2025 | GEF: A GNN-Based Evaluation Framework for FPGA Routing Architecture. | Yuanqi Wang, Yunfei Dai, Jiangnan Li, Kaixiang Zhu, Huizhen Kuang, Hao Zhou, Eric Ren, Xifan Tang, Weijun Qin, Tao Li, Lingli Wang |
| 2025 | Connection Tracking at 400 Gbps. | David Vodk, Oliver Gurka, Jir Matousek, Daniel Kondys |
| 2025 | SparseDPD: A Sparse Neural Network-Based Digital Predistortion FPGA Accelerator for RF Power Amplifier Linearization. | Manno Versluis, Yizhuo Wu, Chang Gao |
| 2025 | DMA Calypte: Open-Source Ultra-Low Latency DMA Engine for FPGAs. | Vladislav Vlek, Martin Spinler, Jakub Cabal, Toms Martnek |
| 2025 | FPGA Stereo Visual Slam with Efficient Stereo Feature Matching and Key-Frame Generation. | Miyuru Thathsara, Damith Anhettigama, Siew-Kei Lam |
| 2025 | Analytical Buffer Sizing for Neural Network Inference Applications on FPGAs. | Lukas Stasytis, Felix Jentzsch, Zsolt Istvn |
| 2025 | Towards Accelerated Healthcare Federated System Through Heterogeneous Accelerators. | Giuseppe Sorrentino, Davide Conficconi |
| 2025 | Four-Input Lookup Table (LUT4) and Architectural Enhancements Enable Power Efficient Mid-Range FPGAs. | Satwant Singh, Michael Schneider, Ziad Aboud, Jonathan Peterson, Senani Gunaratna, Ting Yew, Cindy Lee, Rick Crotty |
| 2025 | FPGA-Based MPSoCs for High-Performance Sensor Fusion: Accelerating Covariance Intersection. | Hazem M. Sharf, Mohamed Hassan |
| 2025 | Programmable Congestion Generator for Evaluating FPGA Interconnect Robustness. | Atreyee Saha, Sandesh Goyal, Aashish Tripathi |
| 2025 | Maximizing Resource Utilization for Stencil Computing. | Pedro Henrique Di Francia Rosso, Guido Araujo |
| 2025 | Multi-FPGA Programming Using OpenMP. | Pedro Henrique Di Francia Rosso, Guido Araujo |
| 2025 | URAM-Based Asynchronous FIFO Design for Improved Throughput and FPGA RAM Usage. | Martim Rosado, Pedro Toms, Nuno Roma, Andr David |