George A. Constantinides
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
143
Venues
21
Active years
1982–2026
Best venue rank
A*
Where they publish
- BFPL45 papers
- NationalFCCM33 papers
- AFPGA25 papers
- CISCAS9 papers
- ADATE5 papers
- CARITH4 papers
- NationalACSSC3 papers
- A*DAC3 papers
- MulticonferenceICASSP3 papers
- ADSN2 papers
- A*HPCA1 paper
- A*EMNLP1 paper
- BFMCAD1 paper
- A*PLDI1 paper
- BASPDAC1 paper
- A*CAV1 paper
- AMobisys1 paper
- A*POPL1 paper
- NationalHiPC1 paper
- CDSD1 paper
- BPIMRC1 paper
Papers
143 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2026 | DATE | Towards Input-Distribution-Aware Approximate Multiplier Generation for CNNs. | Alessandro Buccolini, Marco Biasion, Rodrigo Otoni, George A. Constantinides, Laura Pozzi |
| 2026 | FCCM | Towards Small Language Models on FPGAs. | Filip Wojcicki, Omar Sharif, Ebby Samson, Paul H. J. Kelly, George A. Constantinides, Christos Bouganis, Wayne Luk |
| 2025 | FCCM | NeuraLUT-Assemble: Hardware-Aware Assembling of Sub-Neural Networks for Efficient LUT Inference. | Marta Andronic, George A. Constantinides |
| 2025 | FCCM | Ph.D. Project Hardware-Aware Neural Networks. | Marta Andronic, George A. Constantinides |
| 2025 | FCCM | Banked Memories for Soft SIMT Processors. | Martin Langhammer, George A. Constantinides |
| 2025 | FPGA | ReducedLUT: Table Decomposition with "Don't Care" Conditions. | Oliver Cassidy, Marta Andronic, Samuel Coward, George A. Constantinides |
| 2025 | FPGA | Greater than the Sum of its LUTs: Scaling Up LUT-based Neural Networks with AmigoLUT. | Olivia Weng, Marta Andronic, Danial Zuberi, Jiaqing Chen, Caleb Geniesse, George A. Constantinides, Nhan Tran, Nicholas J. Fraser, Javier Mauricio Duarte, Ryan Kastner |
| 2025 | HPCA | BitMoD: Bit-serial Mixture-of-Datatype LLM Acceleration. | Yuzong Chen, Ahmed F. AbouElhamayed, Xilai Dai, Yang Wang, Marta Andronic, George A. Constantinides, Mohamed S. Abdelfattah |
| 2024 | ARITH | Combining Power and Arithmetic Optimization via Datapath Rewriting. | Samuel Coward, Theo Drane, Emiliano Morini, George A. Constantinides |
| 2024 | FPGA | A Statically and Dynamically Scalable Soft GPGPU. | Martin Langhammer, George A. Constantinides |
| 2024 | FPL | NeuraLUT: Hiding Neural Network Density in Boolean Synthesizable Functions. | Marta Andronic, George A. Constantinides |
| 2024 | FPL | Exploring FPGA designs for MX and beyond. | Ebby Samson, Naveen Mellempudi, Wayne Luk, George A. Constantinides |
| 2023 | ACSSC | Multiplier Optimization via E-Graph Rewriting. | Andy Wanna, Samuel Coward, Theo Drane, George A. Constantinides, Milos D. Ercegovac |
| 2023 | DAC | Automating Constraint-Aware Datapath Optimization using E-Graphs. | Samuel Coward, George A. Constantinides, Theo Drane |
| 2023 | DSN | A Parametrizable Template for Approximate Logic Synthesis. | Morteza Rezaalipour, Marco Biasion, Ilaria Scarabottolo, George A. Constantinides, Laura Pozzi |
| 2023 | DSN | Multi-Metric SMT-Based Evaluation of Worst-Case-Error for Approximate Circuits. | Morteza Rezaalipour, Lorenzo Ferretti, Ilaria Scarabottolo, George A. Constantinides, Laura Pozzi |
| 2023 | EMNLP | Revisiting Block-based Quantisation: What is Important for Sub-8-bit LLM Inference? | Cheng Zhang, Jianyi Cheng, Ilia Shumailov, George A. Constantinides, Yiren Zhao |
| 2023 | FCCM | ATHEENA: A Toolflow for Hardware Early-Exit Network Automation. | Benjamin Biggs, Christos-Savvas Bouganis, George A. Constantinides |
| 2023 | FMCAD | Datapath Verification via Word-Level E-Graph Rewriting. | Samuel Coward, Emiliano Morini, Bryan Tan, Theo Drane, George A. Constantinides |
| 2023 | FPL | eGPU: A 750 MHz Class Soft GPGPU for FPGA. | Martin Langhammer, George A. Constantinides |
| 2023 | PLDI | Combining E-Graphs with Abstract Interpretation. | Samuel Coward, George A. Constantinides, Theo Drane |
| 2022 | ARITH | Automatic Datapath Optimization using E-Graphs. | Samuel Coward, George A. Constantinides, Theo Drane |
| 2022 | FCCM | Dynamic C-Slow Pipelining for HLS. | Jianyi Cheng, John Wickerson, George A. Constantinides |
| 2022 | FPGA | Finding and Finessing Static Islands in Dynamically Scheduled Circuits. | Jianyi Cheng, John Wickerson, George A. Constantinides |
| 2022 | FPGA | Logic Shrinkage: Learned FPGA Netlist Sparsity for Efficient Neural Network Inference. | Erwei Wang, James J. Davis, Georgios-Ilias Stavrou, Peter Y. K. Cheung, George A. Constantinides, Mohamed S. Abdelfattah |
| 2022 | FPL | Dynamic Inter-Block Scheduling for HLS. | Jianyi Cheng, Lana Josipovic, George A. Constantinides, John Wickerson |
| 2022 | FPL | POLSCA: Polyhedral High-Level Synthesis with Compiler Transformations. | Ruizhe Zhao, Jianyi Cheng, Wayne Luk, George A. Constantinides |
| 2021 | ASPDAC | Learning Boolean Circuits from Examples for Approximate Logic Synthesis. | Sina Boroumand, Christos-Savvas Bouganis, George A. Constantinides |
| 2021 | CAV | Rigorous Roundoff Error Analysis of Probabilistic Floating-Point Computations. | George A. Constantinides, Fredrik Dahlqvist, Zvonimir Rakamaric, Rocco Salvia |
| 2021 | FCCM | Probabilistic Scheduling in High-Level Synthesis. | Jianyi Cheng, John Wickerson, George A. Constantinides |
| 2021 | FPGA | Probabilistic Optimization for High-Level Synthesis. | Jianyi Cheng, John Wickerson, George A. Constantinides |
| 2021 | FPL | Exploiting the Correlation between Dependence Distance and Latency in Loop Pipelining for HLS. | Jianyi Cheng, John Wickerson, George A. Constantinides |
| 2021 | Mobisys | Enabling Binary Neural Network Training on the Edge. | Erwei Wang, James J. Davis, Daniele Moro, Piotr Zielinski, Jia Jie Lim, Claudionor Coelho, Satrajit Chatterjee, Peter Y. K. Cheung, George A. Constantinides |
| 2020 | FPGA | Combining Dynamic & Static Scheduling in High-level Synthesis. | Jianyi Cheng, Lana Josipovic, George A. Constantinides, Paolo Ienne, John Wickerson |
| 2020 | FPL | Precise Pointer Analysis in High-Level Synthesis. | Nadesh Ramanathan, George A. Constantinides, John Wickerson |
| 2019 | ACSSC | A Probabilistic Approach to Floating-Point Arithmetic. | Fredrik Dahlqvist, Rocco Salvia, George A. Constantinides |
| 2019 | DAC | Partition and Propagate: an Error Derivation Algorithm for the Design of Approximate Circuits. | Ilaria Scarabottolo, Giovanni Ansaloni, George A. Constantinides, Laura Pozzi |
| 2019 | FCCM | Formalizing Loop-Carried Dependencies in Coq for High-Level Synthesis. | Florian Faissole, George A. Constantinides, David B. Thomas |
| 2019 | FCCM | LUTNet: Rethinking Inference in FPGA Soft Logic. | Erwei Wang, James J. Davis, Peter Y. K. Cheung, George A. Constantinides |
| 2019 | FPGA | EASY: Efficient Arbiter SYnthesis from Multi-threaded Code. | Jianyi Cheng, Shane T. Fleming, Yu Ting Chen, Jason Helge Anderson, George A. Constantinides |
| 2018 | ARITH | A High Throughput Polynomial and Rational Function Approximations Evaluator. | Nicolas Brisebarre, George A. Constantinides, Milos Ercezovac, Silviu-Ioan Filip, Matei Istoan, Jean-Michel Muller |
| 2018 | ARITH | Digit Elision for Arbitrary-accuracy Iterative Computation. | He Li, James J. Davis, John Wickerson, George A. Constantinides |
| 2018 | FCCM | Concurrency-Aware Thread Scheduling for High-Level Synthesis. | Nadesh Ramanathan, George A. Constantinides, John Wickerson |
| 2018 | FPL | An Efficient FPGA-based Axis-Aligned Box Tool for Embedded Computer Graphics. | Georgios Chatzianastasiou, George A. Constantinides |
| 2017 | ACSSC | Run fast when you can: Loop pipelining with uncertain and non-uniform memory dependencies. | Junyi Liu, John Wickerson, Samuel Bayliss, George A. Constantinides |
| 2017 | DATE | Quantifying error: Extending static timing analysis with probabilistic transitions. | Kevin E. Murray, Andrea Suardi, Vaughn Betz, George A. Constantinides |
| 2017 | FPGA | FPGAs in the Cloud. | George A. Constantinides |
| 2017 | FPGA | Hardware Synthesis of Weakly Consistent C Concurrency. | Nadesh Ramanathan, Shane T. Fleming, John Wickerson, George A. Constantinides |
| 2017 | FPL | STRIPE: Signal selection for runtime power estimation. | James J. Davis, Joshua M. Levine, Edward A. Stott, Eddie Hung, Peter Y. K. Cheung, George A. Constantinides |
| 2017 | FPL | Tile size selection for optimized memory reuse in high-level synthesis. | Junyi Liu, John Wickerson, George A. Constantinides |
| 2017 | POPL | Automatically comparing memory consistency models. | John Wickerson, Mark Batty, Tyler Sorensen, George A. Constantinides |
| 2016 | FCCM | KAPow: A System Identification Approach to Online Per-Module Power Estimation in FPGA Designs. | Eddie Hung, James J. Davis, Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung, George A. Constantinides |
| 2016 | FCCM | Loop Splitting for Efficient Pipelining in High-Level Synthesis. | Junyi Liu, John Wickerson, George A. Constantinides |
| 2016 | FPGA | Knowledge is Power: Module-level Sensing for Runtime Optimisation (Abstact Only). | James J. Davis, Eddie Hung, Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung, George A. Constantinides |
| 2016 | FPGA | Automatically Optimizing the Latency, Area, and Accuracy of C Programs for High-Level Synthesis. | Xitong Gao, John Wickerson, George A. Constantinides |
| 2016 | FPGA | A Case for Work-stealing on FPGAs with OpenCL Atomics. | Nadesh Ramanathan, John Wickerson, Felix Winterstein, George A. Constantinides |
| 2016 | HiPC | Balancing Locality and Concurrency: Solving Sparse Triangular Systems on GPUs. | Andrea Picciau, Gordon E. Inggs, John Wickerson, Eric C. Kerrigan, George A. Constantinides |
| 2015 | DATE | Transparent linking of compiled software and synthesized hardware. | David B. Thomas, Shane T. Fleming, George A. Constantinides, Dan R. Ghica |
| 2015 | FCCM | Offline Synthesis of Online Dependence Testing: Parametric Loop Pipelining for HLS. | Junyi Liu, Samuel Bayliss, George A. Constantinides |
| 2015 | FPGA | System-level Linking of Synthesised Hardware and Compiled Software Using a Higher-order Type System. | Shane T. Fleming, David B. Thomas, George A. Constantinides, Dan R. Ghica |
| 2015 | FPGA | Numerical Program Optimization for High-Level Synthesis. | Xitong Gao, George A. Constantinides |
| 2015 | FPGA | Delay-Bounded Routing for Shadow Registers. | Eddie Hung, Joshua M. Levine, Edward A. Stott, George A. Constantinides, Wayne Luk |
| 2015 | FPGA | MATCHUP: Memory Abstractions for Heap Manipulating Programs. | Felix Winterstein, Kermin Fleming, Hsin-Jung Yang, Samuel Bayliss, George A. Constantinides |
| 2015 | FPL | PushPush: Seamless integration of hardware and software objects via function calls over AXI. | Shane T. Fleming, Ivan Beretta, David B. Thomas, George A. Constantinides, Dan R. Ghica |
| 2014 | DAC | Datapath Synthesis for Overclocking: Online Arithmetic for Latency-Accuracy Trade-offs. | Kan Shi, David Boland, Edward A. Stott, Samuel Bayliss, George A. Constantinides |
| 2014 | FCCM | Compiling Higher Order Functional Programs to Composable Digital Hardware. | Eduardo Aguilar-Pelaez, Samuel Bayliss, Alex I. Smith, Felix Winterstein, Dan R. Ghica, David B. Thomas, George A. Constantinides |
| 2014 | FCCM | Separation Logic-Assisted Code Transformations for Efficient High-Level Synthesis. | Felix Winterstein, Samuel Bayliss, George A. Constantinides |
| 2014 | FPL | Area implications of memory partitioning for high-level synthesis on FPGAs. | Luca Gallo, Alessandro Cilardo, David B. Thomas, Samuel Bayliss, George A. Constantinides |
| 2014 | FPL | FPGA implementation of an interior point method for high-speed model predictive control. | Junyi Liu, Helfried Peyrl, Andreas Burg, George A. Constantinides |
| 2013 | FCCM | Application Composition and Communication Optimization in Iterative Solvers Using FPGAs. | Abid Rafique, Nachiket Kapre, George A. Constantinides |
| 2013 | FCCM | Accuracy-Performance Tradeoffs on an FPGA through Overclocking. | Kan Shi, David Boland, George A. Constantinides |
| 2013 | FPGA | Word-length optimization beyond straight line code. | David Boland, George A. Constantinides |
| 2013 | FPL | A variation-adaptive retiming method exploiting reconfigurability. | Zhenyu Guan, Justin S. J. Wong, Sumanta Chaudhuri, George A. Constantinides, Peter Y. K. Cheung |
| 2013 | FPL | SMI: Slack Measurement Insertion for online timing monitoring in FPGAs. | Joshua M. Levine, Edward A. Stott, George A. Constantinides, Peter Y. K. Cheung |
| 2013 | FPL | FPGA-based K-means clustering using tree-based data structures. | Felix Winterstein, Samuel Bayliss, George A. Constantinides |
| 2013 | ISCAS | Overclocking datapath for latency-error tradeoff. | Kan Shi, David Boland, George A. Constantinides |
| 2012 | FCCM | Fixed Point Lanczos: Sustaining TFLOP-equivalent Performance in FPGAs for Scientific Computing. | Juan Luis Jerez, George A. Constantinides, Eric C. Kerrigan |
| 2012 | FCCM | Online Measurement of Timing in Circuits: For Health Monitoring and Dynamic Voltage & Frequency Scaling. | Joshua M. Levine, Edward A. Stott, George A. Constantinides, Peter Y. K. Cheung |
| 2012 | FPGA | Optimizing SDRAM bandwidth for custom FPGA loop accelerators. | Samuel Bayliss, George A. Constantinides |
| 2012 | FPGA | A scalable approach for automated precision analysis. | David Boland, George A. Constantinides |
| 2012 | FPL | A two-stage variation-aware placement method for FPGAS exploiting variation maps classification. | Zhenyu Guan, Justin S. J. Wong, Sumanta Chaudhuri, George A. Constantinides, Peter Y. K. Cheung |
| 2012 | FPL | Enhancing performance of Tall-Skinny QR factorization using FPGAs. | Abid Rafique, Nachiket Kapre, George A. Constantinides |
| 2012 | ISCAS | Correctly rounded constant integer division via multiply-add. | Theo Drane, Wai-chuen Cheung, George A. Constantinides |
| 2011 | DATE | Optimisation of mutually exclusive arithmetic sum-of-products. | Theo Drane, George A. Constantinides |
| 2011 | FPGA | An FPGA implementation of a sparse quadratic programming solver for constrained predictive control. | Juan Luis Jerez, George A. Constantinides, Eric C. Kerrigan |
| 2011 | FPGA | Health monitoring of live circuits in FPGAs based on time delay measurement (abstract only). | Joshua M. Levine, Edward A. Stott, George A. Constantinides, Peter Y. K. Cheung |
| 2010 | DSD | Customizable Composition and Parameterization of Hardware Design Transformations. | Tim Todman, Qiang Liu, Wayne Luk, George A. Constantinides |
| 2010 | FCCM | Automated Precision Analysis: A Polynomial Algebraic Approach. | David Boland, George A. Constantinides |
| 2010 | FCCM | A Scripting Engine for Combining Design Transformations. | Tim Todman, Qiang Liu, Wayne Luk, George A. Constantinides |
| 2010 | FPL | Mapping Multiple Multivariate Gaussian Random Number Generators on an FPGA. | Chalermpol Saiprasert, Christos-Savvas Bouganis, George A. Constantinides |
| 2009 | FCCM | More Flops or More Precision? Accuracy Parameterizable Linear Equation Solvers for Model Predictive Control. | Antonio Roldao Lopes, Amir Shahzad, George A. Constantinides, Eric C. Kerrigan |
| 2009 | FPL | Optimising designs by combining model-based and pattern-based transformations. | Qiang Liu, Tim Todman, Jos Gabriel de Figueiredo Coutinho, Wayne Luk, George A. Constantinides |
| 2009 | FPL | Area estimation and optimisation of FPGA routing fabrics. | Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung |
| 2008 | FPL | An FPGA-based implementation of the MINRES algorithm. | David Boland, George A. Constantinides |
| 2008 | FPL | Combining data reuse exploitationwith data-level parallelization for FPGA targeted hardware compilation: A geometric programming framework. | Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung |
| 2008 | ISCAS | Glitch-aware output switching activity from word-level statistics. | Jonathan A. Clarke, George A. Constantinides, Peter Y. K. Cheung, Alastair M. Smith |
| 2007 | FCCM | A Hybrid Memory Sub-system for Video Coding Applications. | Su-Shin Ang, George A. Constantinides, Wayne Luk, Peter Y. K. Cheung |
| 2007 | FCCM | Automatic On-chip Memory Minimization for Data Reuse. | Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung |
| 2007 | FPL | A floating-point Extended Kalman Filter implementation for autonomous mobile robots. | Vanderlei Bonato, Eduardo Marques, George A. Constantinides |
| 2007 | FPL | On the feasibility of early routing capacitance estimation for FPGAs. | Jonathan A. Clarke, George A. Constantinides, Peter Y. K. Cheung |
| 2007 | PIMRC | CCDF and Monte Carlo Analysis of a Digital Polar Transmitter for Ultra-Wideband System. | Kwang-Hwee Seah, Michael Yan Wah Chia, Christos Papavassiliou, George A. Constantinides |
| 2006 | FCCM | A Novel Hueristic and Provable Bounds for Reconfigurable Architecture Design. | Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung |
| 2006 | FPGA | Yield enhancements of design-specific FPGAs. | Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko |
| 2006 | FPL | Dynamic Memory Sub-System for Reconfigurable Platforms. | Su-Shin Ang, George A. Constantinides |
| 2006 | FPL | Reconfiguration and Fine-Grained Redundancy for Fault Tolerance in FPGAs. | Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko |
| 2006 | FPL | High-Level Power Optimization for Digital Signal Processing in Reconfigurable Logic. | Jonathan A. Clarke, George A. Constantinides |
| 2006 | FPL | Data Reuse Exploration for FPGA Based Platforms Applied to the Full Search Motion Estimation Algorithm. | Konstantinos Masselos, George A. Constantinides, Qiang Liu |
| 2006 | FPL | A Novel Heuristic and Provable Bounds for Reconfigurable Architecture Design. | Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung |
| 2006 | FPL | FPGA Based Acceleration of the Linpack Benchmark: A High Level Code Transformation Approach. | Kieron Turkington, Konstantinos Masselos, George A. Constantinides, Philip Heng Wai Leong |
| 2006 | ISCAS | Fast word-level power models for synthesis of FPGA-based arithmetic. | Jonathan A. Clarke, Altaf Abdul Gaffar, George A. Constantinides, Peter Y. K. Cheung |
| 2005 | FCCM | A Novel 2D Filter Design Methodology for Heterogeneous Devices. | Christos-Savvas Bouganis, George A. Constantinides, Peter Y. K. Cheung |
| 2005 | FPGA | Analysis of yield loss due to random photolithographic defects in the interconnect structure of FPGAs. | Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko |
| 2005 | FPGA | Exploration of heterogeneous reconfigurable architectures (abstract only). | Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung |
| 2005 | FPL | Heterogeneity Exploration for Multiple 2D Filter Designs. | Christos-Savvas Bouganis, Peter Y. K. Cheung, George A. Constantinides |
| 2005 | FPL | Yield modelling and Yield Enhancement for FPGAs using Fault Tolerance Schemes. | Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko |
| 2005 | FPL | Parameterized Logic Power Consumption Models for FPGA based Systems. | Jonathan A. Clarke, Altaf Abdul Gaffar, George A. Constantinides |
| 2005 | FPL | Error Modelling of Dual FiXed-point Arithmetic and its Application in Field Programmable Logic. | Chun Te Ewe, Peter Y. K. Cheung, George A. Constantinides |
| 2005 | FPL | Using DSP Blocks For ROM Replacement: A Novel Synthesis Flow. | Gareth W. Morris, George A. Constantinides, Peter Y. K. Cheung |
| 2005 | FPL | FPGA-Accelerated Reconstruction of Gene Regulatory Networks. | Iosifina Pournara, Christos-Savvas Bouganis, George A. Constantinides |
| 2005 | FPL | Power and Area Optimization for Multiple Restricted Multiplication. | Nalin Sidahao, George A. Constantinides, Peter Y. K. Cheung |
| 2005 | FPL | An Analytical Approach to Generation and Exploration of Reconfigurable Architectures. | Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung |
| 2005 | ISCAS | A novel 2D filter design methodology. | Christos-Savvas Bouganis, George A. Constantinides, Peter Y. K. Cheung |
| 2005 | ISCAS | A heuristic approach for multiple restricted multiplication. | Nalin Sidahao, George A. Constantinides, Peter Y. K. Cheung |
| 2004 | FCCM | Word-Length Optimization of Folded Polynomial Evaluation. | George A. Constantinides, Abunaser Miah, Nalin Sidahao |
| 2004 | FCCM | Migrating Functionality from ROMS to Embedded Multipliers. | Gareth W. Morris, George A. Constantinides, Peter Y. K. Cheung |
| 2004 | FCCM | A Structured System Methodology for FPGA Based System-on-A-Chip Design. | N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk |
| 2004 | FPL | Dual Fixed-Point: An Efficient Alternative to Floating-Point Computation. | Chun Te Ewe, Peter Y. K. Cheung, George A. Constantinides |
| 2004 | FPL | A Structured Methodology for System-on-an-FPGA Design. | N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk |
| 2004 | FPL | Multiple Restricted Multiplication. | Nalin Sidahao, George A. Constantinides, Peter Y. K. Cheung |
| 2003 | FCCM | Perturbation Analysis for Word-length Optimization. | George A. Constantinides |
| 2003 | FPL | A Reconfigurable Platform for Real-Time Embedded Video Image Processing. | N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk |
| 2003 | ISCAS | Architectures for function evaluation on FPGAs. | Nalin Sidahao, George A. Constantinides, Peter Y. K. Cheung |
| 2002 | FCCM | Optimum Wordlength Allocation. | George A. Constantinides, Peter Y. K. Cheung, Wayne Luk |
| 2001 | DATE | Heuristic datapath allocation for multiple wordlength systems. | George A. Constantinides, Peter Y. K. Cheung, Wayne Luk |
| 2001 | FCCM | The Multiple Wordlength Paradigm. | George A. Constantinides, Peter Y. K. Cheung, Wayne Luk |
| 2000 | FCCM | Multiple Precision for Resource Minimization. | George A. Constantinides, Peter Y. K. Cheung, Wayne Luk |
| 2000 | FPL | Multiple-Wordlength Resource Binding. | George A. Constantinides, Peter Y. K. Cheung, Wayne Luk |
| 2000 | ISCAS | Roundoff-noise shaping in filter design. | George A. Constantinides, Peter Y. K. Cheung, Wayne Luk |
| 2000 | ISCAS | Active filter synthesis based on tuneable log-domain lossy integrators. | Nikos Fragoulis, Ioannis Haritantis, George A. Constantinides |
| 1999 | FPL | Untitled record | George A. Constantinides, Peter Y. K. Cheung, Wayne Luk |
| 1991 | ICASSP | Layered DCT video coding for embedded data transmission over BISDN. | D. K. Mitrakos, George A. Constantinides |
| 1983 | ICASSP | Maximum likelihood estimation of composite source models for image coding. | D. K. Mitrakos, George A. Constantinides |
| 1982 | ICASSP | Composite source coding techniques for image bandwidth compression. | D. K. Mitrakos, George A. Constantinides |