| 2026 | Chrono-Fabric: A Decoupled Hierarchical Framework for Cycle-Accurate Coordination in Multi-FPGA Systems. | Congwu Zhang, Panyu Wang, Yazhou Wang, Bibo Yang, Mingyu Chen, Yungang Bao, Ke Zhang |
| 2026 | HERA: A Bandwidth-efficient Accelerator for Fully Homomorphic Encryption on HBM-enabled FPGA. | Zhihan Xu, Rajgopal Kannan, Viktor K. Prasanna |
| 2026 | Hardware Software Optimizations for Fast Model Recovery on Reconfigurable Architectures (FPGAs) for Edge and Physical AI. | Bin Xu, Ayan Banerjee, Sandeep K. S. Gupta |
| 2026 | UDP: A Universal DSP Packing Framework for Low-bitwidth MAC Acceleration on FPGAs. | Jundong Wu, Zhendong Zheng, Lei Gong, Chao Wang, Xuehai Zhou |
| 2026 | Modulation Recognition in a System-on-Chip. | John Wohlbier, Daniel Bonness, Jodi Miller, Marika Schubert |
| 2026 | A Model-Hardware Co-design Framework for Robust and Efficient CNN-Based SAR ATR. | Sachini Wickramasinghe, Tian Ye, Cauligi S. Raghavendra, Viktor K. Prasanna |
| 2026 | TDM Signal Grouping and Package Pin Assignment for 2.5D Multi-FPGA Systems with Lookahead Placement. | Jiarui Wang, Runzhe Tao, Jing Mai, Xun Jiang, Shenghua Wang, Cuiliu Yang, Haoyu Jie, Kan Huang, Richard Y. Sun, Yibo Lin |
| 2026 | A Cloud-Native FPGA-Accelerated Framework and Methodology for Hardware Verification. | Irfan Waheed, Wajahat Riaz, Babar Sohail |
| 2026 | Multi-Port Memory with Bidirectional Ports for FPGAs Using XOR and LVT Methods. | Kevin Townsend |
| 2026 | Hardware Accelerated FPGA Divide-and-Conquer Page Placement in Milliseconds. | Ezra Thomas, Jing Li, Andr DeHon |
| 2026 | Striking the Balance: GEMM Performance Optimization Across Generations of Ryzen™ AI NPUs. | Endri Taka, Andre Roesti, Joseph Melber, Pranathi Vasireddy, Kristof Denolf, Diana Marculescu |
| 2026 | HGQ: High Granularity Quantization for Real-time Neural Networks on FPGAs. | Chang Sun, Zhiqiang Que, Thea Aarrestad, Vladimir Loncar, Jennifer Ngadiuba, Wayne Luk, Maria Spiropulu |
| 2026 | Closing the Loop on FPGA Verification: An Iterative Framework for Maximizing Routing Resource Coverage. | Ruthwik Reddy Sunketa, Aman Arora |
| 2026 | EdgeSort: A Sub-100 ns, Line-Rate FPGA Streaming Sorter. | Greg Stitt, Wesley Piard, Christopher Crary |
| 2026 | SORCERI: Streaming Overlay Acceleration for Highly Contracted Electron Repulsion Integral Computations in Quantum Chemistry. | Philip Stachura, Xin Wu, Christian Plessl, Zhenman Fang |
| 2026 | Chext: A Domain-specific Language for Safe and Agile Elastic Dataflow Accelerators. | Canberk Snmez, Mohamed Shahawy, Paolo Ienne |
| 2026 | OpenPCIe: An Open-Source PCIe Controller. | Idris Somoye, David Jovel, Lamia Mannan |
| 2026 | A High-level Synthesis Toolchain for the Julia Language. | Benedict Short, Ian McInerney, John Wickerson |
| 2026 | CAD-in-the-Cloud: Protecting FPGA Design Privacy via Redacted Netlists. | Eddie Rydell, Reilly McKendrick, Jeffrey Goeders |
| 2026 | Hyperscale FPGA Engineering Systems at Microsoft. | Rob Rydberg, Madison N. Emas, John Demme, Ana Ibarra, Kara Kagi, Brandon Klouchek, Abhijeet Lawande, Todd Massengill, David J. Powers, Andrew Putnam |
| 2026 | Towards Scheduling of Pipelined Dataflow Graphs in MLIR. | Gabriel Rodriguez-Canal, Nicolas Bohm Agostini, Ankur Limaye, Vito Giovanni Castellana, Joseph B. Manzano, Antonino Tumeo, Maurice Jamieson, Nick Brown |
| 2026 | HACE: HLS-Tool-Agnostic CDFG Extraction from RTL Designs. | Carmine Rizzi, Sebastian Pfeiler, Lana Josipovic |
| 2026 | FARE: A Fine-grained Pipelined Reconfigurable FlashAttention Kernel. | Kaushikkumar S. Rathva, Aakarsh Alam, Srini Srinivasan, Sumit K. Mandal |
| 2026 | TeLLMe: An Efficient End-to-End Ternary LLM Prefill and Decode Accelerator with Table-Lookup Matmul on Edge FPGAs. | Ye Qiao, Zhiheng Chen, Yifan Zhang, Yian Wang, Sitao Huang |
| 2026 | A Hierarchical Methodology for Hardware Design Comparison in HPC Workloads. | Doru-Thom Popovici, Mario Vega, Angelos Ioannou, Fabien Chaix, Dania Susanne Mosuli, Blair Reasoner, Tan Nguyen, Xiaokun Yang, John Shalf |