| 2025 | ACL | A Fully Generative Motivational Interviewing Counsellor Chatbot for Moving Smokers Towards the Decision to Quit. | Zafarullah Mahmood, Soliman Ali, Jiading Zhu, Mohamed Abdelwahab, Michelle Yu Collins, Sihan Chen, Yi Cheng Zhao, Jodi Wolff, Osnat C. Melamed, Nadia Minian, Marta Maslej, Carolynne Cooper, Matt Ratto, Peter Selby, Jonathan Rose |
| 2024 | EACL | Generation, Distillation and Evaluation of Motivational Interviewing-Style Reflections with a Foundational Language Model. | Andrew Brown, Jiading Zhu, Mohamed Abdelwahab, Alec Dong, Cindy Wang, Jonathan Rose |
| 2020 | ICPR | Detection and Correspondence Matching of Corneal Reflections for Eye Tracking Using Deep Learning. | Soumil Chugh, Braiden Brousseau, Jonathan Rose, Moshe Eizenman |
| 2018 | FPL | Automatic Topology Optimization for FPGA Interconnect Synthesis. | Alex Rodionov, Jonathan Rose |
| 2017 | FPGA | Synchronization Constraints for Interconnect Synthesis. | Alex Rodionov, Jonathan Rose |
| 2016 | FCCM | High Performance Instruction Scheduling Circuits for Out-of-Order Soft Processors. | Henry Wong, Vaughn Betz, Jonathan Rose |
| 2015 | FPGA | Fine-Grained Interconnect Synthesis. | Alex Rodionov, David Biancolin, Jonathan Rose |
| 2014 | FCCM | On Hard Adders and Carry Chains in FPGAs. | Jason Luu, Conor McCullough, Sen Wang, Safeen Huda, Bo Yan, Charles Chiasson, Kenneth B. Kent, Jason Helge Anderson, Jonathan Rose, Vaughn Betz |
| 2014 | FPGA | Towards interconnect-adaptive packing for FPGAs. | Jason Luu, Jonathan Rose, Jason Helge Anderson |
| 2012 | FPGA | The VTR project: architecture and CAD for FPGAs from verilog to routing. | Jonathan Rose, Jason Luu, Chi Wai Yu, Opal Densmore, Jeffrey Goeders, Andrew Somerville, Kenneth B. Kent, Peter Jamieson, Jason Helge Anderson |
| 2012 | FPL | On the difficulty of pin-to-wire routing in FPGAs. | Niyati Shah, Jonathan Rose |
| 2011 | FPGA | Architecture description and packing for logic blocks with hierarchy, modes and complex interconnect. | Jason Luu, Jason Helge Anderson, Jonathan Rose |
| 2011 | FPGA | The role of FPGAs in a converged future with heterogeneous programmable processors: pre-conference workshop. | Jonathan Rose, Guy G. Lemieux |
| 2011 | FPGA | Comparing FPGA vs. custom cmos and the impact on processor microarchitecture. | Henry Wong, Vaughn Betz, Jonathan Rose |
| 2009 | CASES | Fine-grain performance scaling of soft vector processors. | Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose |
| 2009 | FCCM | FPGA-based Monte Carlo Computation of Light Absorption for Photodynamic Cancer Therapy. | Jason Luu, Keith Redmond, William Lo, Paul Chow, Lothar Lilge, Jonathan Rose |
| 2009 | FPGA | VPR 5.0: FPGA cad and architecture exploration tools with single-driver routing, heterogeneity and process scaling. | Jason Luu, Ian Kuon, Peter Jamieson, Ted Campbell, Andy Gean Ye, Wei Mark Fang, Jonathan Rose |
| 2009 | FPGA | Soft vector processors vs FPGA custom hardware: measuring and reducing the gap. | Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose |
| 2009 | FPL | The evolution of architecture exploration of programmable devices. | Jonathan Rose |
| 2009 | FPL | Data parallel FPGA workloads: Software versus hardware. | Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose |
| 2008 | CASES | VESPA: portable, scalable, and flexible FPGA-based vector processors. | Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose |
| 2008 | DAC | Automated transistor sizing for FPGA architecture exploration. | Ian Kuon, Jonathan Rose |
| 2008 | FPGA | Modeling routing demand for early-stage FPGA architecture development. | Wei Mark Fang, Jonathan Rose |
| 2008 | FPGA | Area and delay trade-offs in the circuit and architecture design of FPGAs. | Ian Kuon, Jonathan Rose |
| 2006 | FPGA | Measuring the gap between FPGAs and ASICs. | Ian Kuon, Jonathan Rose |
| 2006 | FPGA | Application-specific customization of soft processor microarchitecture. | Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose |
| 2005 | CASES | The microarchitecture of FPGA-based soft processors. | Peter Yiannacouras, Jonathan Rose, J. Gregory Steffan |
| 2005 | FPGA | Design, layout and verification of an FPGA using automated tools. | Ian Kuon, Aaron Egier, Jonathan Rose |
| 2005 | FPGA | The Stratix II logic and routing architecture. | David M. Lewis, Elias Ahmed, Gregg Baeckler, Vaughn Betz, Mark Bourgeault, David Cashman, David R. Galloway, Mike Hutton, Christopher Lane, Andy Lee, Paul Leventis, Sandy Marquardt, Cameron McClintock, Ketan Padalia, Bruce Pedersen, Giles Powell, Boris Ratchev, Srinivas Reddy, Jay Schleicher, Kevin Stevens, Richard Yuan, Richard Cliff, Jonathan Rose |
| 2005 | FPGA | Using bus-based connections to improve field-programmable gate array density for implementing datapath circuits. | Andy Gean Ye, Jonathan Rose |
| 2005 | FPL | A Verilog RTL Synthesis Tool for Heterogeneous FPGAs. | Peter Jamieson, Jonathan Rose |
| 2005 | FPL | Measuring and Utilizing the Correlation Between Signal Connectivity and Signal Positioning for FPGAs Containing Multi-Bit Building Blocks. | Andy Gean Ye, Jonathan Rose |
| 2004 | FPGA | A synthesis oriented omniscient manual editor. | Tomasz S. Czajkowski, Jonathan Rose |
| 2004 | FPGA | Transistor grouping and metal layer trade-offs in automatic tile layout of FPGAs. | Ian Kuon, Aaron Egier, Jonathan Rose |
| 2004 | FPL | Hardware Accelerated Novel Protein Identification. | Anish Alex, Jonathan Rose, Ruth Isserlin-Weinberger, Christopher W. V. Hogue |
| 2003 | CVPR | Video-Rate Stereo Depth Measurement on Programmable Hardware. | Ahmad Darabiha, Jonathan Rose, W. James MacLean |
| 2003 | FPGA | Synthetic circuit generation using clustering and iteration. | Paul D. Kundarewich, Jonathan Rose |
| 2003 | FPGA | The Stratix | David M. Lewis, Vaughn Betz, David Jefferson, Andy Lee, Christopher Lane, Paul Leventis, Sandy Marquardt, Cameron McClintock, Bruce Pedersen, Giles Powell, Srinivas Reddy, Chris Wysocki, Richard Cliff, Jonathan Rose |
| 2003 | FPGA | Automatic transistor and physical design of FPGA tiles from an architectural specification. | Ketan Padalia, Ryan Fung, Mark Bourgeault, Aaron Egier, Jonathan Rose |
| 2002 | FPGA | EVE: a CAD tool for manual placement and pipelining assistance of FPGA circuits. | William Chow, Jonathan Rose |
| 2001 | DAC | Panel: (When) Will FPGAs Kill ASICs? | Rob A. Rutenbar, Max Baron, Thomas Daniel, Rajeev Jayaraman, Zvi Or-Bach, Jonathan Rose, Carl Sechen |
| 2001 | FPGA | Mixing buffers and pass transistors in FPGA routing architectures. | Mike Sheng, Jonathan Rose |
| 2000 | FPGA | The effect of LUT and cluster size on deep-submicron FPGA performance and density. | Elias Ahmed, Jonathan Rose |
| 2000 | FPGA | Automatic generation of FPGA routing architectures from high-level descriptions. | Vaughn Betz, Jonathan Rose |
| 2000 | FPGA | Timing-driven placement for FPGAs. | Alexander Marquardt, Vaughn Betz, Jonathan Rose |
| 2000 | FPGA | Real-time, frame-rate face detection on a configurable hardware system (poster abstract). | Rob McCready, Jonathan Rose |
| 1999 | FPGA | FPGA Routing Architecture: Segmentation and Buffering to Optimize Speed and Density. | Vaughn Betz, Jonathan Rose |
| 1999 | FPGA | Using Cluster-Based Logic Blocks and Timing-Driven Packing to Improve FPGA Speed and Density. | Alexander Marquardt, Vaughn Betz, Jonathan Rose |
| 1999 | FPGA | Trading Quality for Compile Time: Ultra-Fast Placement for FPGAs. | Yaska Sankar, Jonathan Rose |
| 1999 | ISCAS | Equivalence classes of clone circuits for physical-design benchmarking. | Michael D. Hutton, Jonathan Rose |
| 1999 | ISCAS | Applications of clone circuits to issues in physical-design. | Michael D. Hutton, Jonathan Rose |
| 1998 | FPGA | A Hybrid Complete-Graph Partial-Crossbar Routing Architecture for Multi-FPGA Systems. | Mohammed A. S. Khalid, Jonathan Rose |
| 1998 | FPGA | Constraints from Hell: How to Tell Makes a Good FPGA (Panel). | Jonathan Rose, Sinan Kaptanoglu, Clive McCarthy, Rob Smith, Sandip Vij, Steve Taylor |
| 1998 | FPGA | A Fast Routability-Driven Router for FPGAs. | Jordan S. Swartz, Vaughn Betz, Jonathan Rose |
| 1997 | FPGA | Generation of Synthetic Sequential Benchmark Circuits. | Michael D. Hutton, Jonathan Rose, Derek G. Corneil |
| 1997 | FPGA | The Transmogrifier-2: A 1 Million Gate Rapid Prototyping System. | David M. Lewis, David R. Galloway, Marcus van Ierssel, Jonathan Rose, Paul Chow |
| 1997 | FPGA | Architectural and Physical Design Challenges for One-Million Gate FPGAs and Beyond. | Jonathan Rose, Dwight D. Hill |
| 1997 | FPGA | Memory-to-Memory Connection Structures in FPGAs with Embedded Memory Arrays. | Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic |
| 1997 | FPL | VPR: A new packing, placement and routing tool for FPGA research. | Vaughn Betz, Jonathan Rose |
| 1996 | DAC | Characterization and Parameterized Random Generation of Digital Circuits. | Michael D. Hutton, Jerry P. Grossman, Jonathan Rose, Derek G. Corneil |
| 1996 | ICCAD | Directional bias and non-uniformity in FPGA global routing architectures. | Vaughn Betz, Jonathan Rose |
| 1995 | FPGA | Using Architectural "Families" to Increase FPGA Speed and Density. | Vaughn Betz, Jonathan Rose |
| 1995 | FPGA | Architecture of Centralized Field-Configurable Memory. | Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic |
| 1994 | ICCAD | Definition and solution of the memory packing problem for field-programmable systems. | David Karchmer, Jonathan Rose |
| 1993 | DAC | Logic Emulation: A Niche or a Future Standard for Design Verification? (Panel Abstract). | Jonathan Rose |
| 1992 | DAC | TEMPT: Technology Mapping for the Exploration of FPGA Architectures with Hard-Wired Connections. | Kevin Chung, Jonathan Rose |
| 1992 | ICCD | Improving FPGA Routing Architectures Using Architecture and CAD Interactions. | Benjamin Tseng, Jonathan Rose, Stephen Brown |
| 1991 | DAC | Chortle-crf: Fast Technology Mapping for Lookup Table-Based FPGAs. | Robert J. Francis, Jonathan Rose, Zvonko G. Vranesic |
| 1991 | DAC | Will the Field-Programmable Gata Array Replace the Mask-Programmable Gate Array? (Panel Abstract). | Jonathan Rose |
| 1991 | ICCAD | Technology Mapping on Lookup Table-Based FPGAs for Performance. | Robert J. Francis, Jonathan Rose, Zvonko G. Vranesic |
| 1990 | DAC | Chortle: A Technology Mapping Program for Lookup Table-Based Field Programmable Gate Arrays. | Robert J. Francis, Jonathan Rose, Kevin Chung |
| 1990 | ICCAD | A Detailed Router for Field-Programmable Gate Arrays. | Stephen Brown, Jonathan Rose, Zvonko G. Vranesic |
| 1988 | DAC | LocusRoute: A Parallel Global Router for Standard Cells. | Jonathan Rose |
| 1988 | ICCAD | Temperature measurement of simulated annealing placements. | Jonathan Rose, Wolfgang Klebsch, Jrgen Wolf |
| 1988 | PPoPP | The Parallel Decomposition and Implementation of an Integrated Circuit Global Router. | Jonathan Rose |