| 2026 | FPGA | HiLFS: FPGA-Orchestrated File System for High-Level Synthesis. | YoungSeok Na, Linus Y. Wong, Andr DeHon, Jing Jane Li |
| 2026 | FPGA | Hardware Accelerated FPGA Divide-and-Conquer Page Placement in Milliseconds. | Ezra Thomas, Jing Li, Andr DeHon |
| 2026 | ISCA | R2d2: Robotized Reconfigurable Network for Disaggregated Datacenters. | Linus Y. Wong, Zhiyao Tang, Justin R. Yu, Zhilei Zheng, Jonathan M. Smith, Andr DeHon, Jing Li |
| 2024 | FPGA | REFINE: Runtime Execution Feedback for INcremental Evolution on FPGA Designs. | Dongjoon Park, Andr DeHon |
| 2022 | ASPLOS | PLD: fast FPGA compilation to make reconfigurable acceleration compatible with modern incremental refinement software development. | Yuanlong Xiao, Eric Micallef, Andrew Butt, Matthew Hofmann, Marc Alston, Matthew Goldsmith, Andrew Merczynski-Hait, Andr DeHon |
| 2022 | FPGA | HiPR: Fast, Incremental Custom Partial Reconfiguration for HLS Developers. | Yuanlong Xiao, Andr DeHon |
| 2022 | FPL | HiPR: High-level Partial Reconfiguration for Fast Incremental FPGA Compilation. | Yuanlong Xiao, Aditya Hota, Dongjoon Park, Andr DeHon |
| 2021 | CCS | Preventing Dynamic Library Compromise on Node.js via RWX-Based Privilege Reduction. | Nikos Vasilakis, Cristian-Alexandru Staicu, Grigoris Ntousakis, Konstantinos Kallas, Ben Karel, Andr DeHon, Michael Pradel |
| 2021 | FCCM | XBERT: Xilinx Logical-Level Bitstream Embedded RAM Transfusion. | Matthew Hofmann, Zhiyao Tang, Jonathan Orgill, Jonathan Nelson, David Glanzman, Brent Nelson, Andr DeHon |
| 2021 | FCCM | HLS-Compatible, Embedded-Processor Stream Links. | Eric Micallef, Yuanlong Xiao, Andr DeHon |
| 2021 | NSDI | Flightplan: Dataplane Disaggregation and Placement for P4 Programs. | Nik Sultana, John Sonchack, Hans Giesen, Isaac Pedisich, Zhaoyang Han, Nishanth Shyamkumar, Shivani Burad, Andr DeHon, Boon Thau Loo |
| 2021 | RAID | μSCOPE: A Methodology for Analyzing Least-Privilege Compartmentalization in Large Software Artifacts. | Nick Roessler, Lucas Atayde, Imani Palmer, Derrick Paul McKee, Jai Pandey, Vasileios P. Kemerlis, Mathias Payer, Adam Bates, Jonathan M. Smith, Andr DeHon, Nathan Dautenhahn |
| 2020 | CoNEXT | DeepMatch: practical deep packet inspection in the data plane using network processors. | Joel Hypolite, John Sonchack, Shlomo Hershkop, Nathan Dautenhahn, Andr DeHon, Jonathan M. Smith |
| 2019 | PLDI | Ignis: scaling distribution-oblivious systems with light-touch distribution. | Nikos Vasilakis, Ben Karel, Yash Palkhiwala, John Sonchack, Andr DeHon, Jonathan M. Smith |
| 2018 | FPL | Case for Fast FPGA Compilation Using Partial Reconfiguration. | Dongjoon Park, Yuanlong Xiao, Nevo Magnezi, Andr DeHon |
| 2018 | NDSS | BreakApp: Automated, Flexible Application Compartmentalization. | Nikos Vasilakis, Ben Karel, Nick Roessler, Nathan Dautenhahn, Andr DeHon, Jonathan M. Smith |
| 2018 | SIGCOMM | In-network computing to the rescue of faulty links. | Hans Giesen, Lei Shi, John Sonchack, Anirudh Chelluri, Nishanth Prabhu, Nik Sultana, Latha A. Kant, Anthony J. McAuley, Alexander Poylisher, Andr DeHon, Boon Thau Loo |
| 2018 | SP | Protecting the Stack with Metadata Policies and Tagged Hardware. | Nick Roessler, Andr DeHon |
| 2017 | FPGA | Quality-Time Tradeoffs in Component-Specific Mapping: How to Train Your Dynamically Reconfigurable Array of Gates with Outrageous Network-delays. | Hans Giesen, Raphael Rubin, Benjamin Gojman, Andr DeHon |
| 2017 | SOSP | Towards Fine-grained, Automated Application Compartmentalization. | Nikos Vasilakis, Ben Karel, Nick Roessler, Nathan Dautenhahn, Andr DeHon, Jonathan M. Smith |
| 2016 | FCCM | Continuous Online Self-Monitoring Introspection Circuitry for Timing Repair by Incremental Partial-Reconfiguration (COSMIC TRIP). | Hans Giesen, Benjamin Gojman, Raphael Rubin, Ji Kim, Andr DeHon |
| 2016 | FCCM | Energy Efficiency of Full Pipelining: A Case Study for Matrix Multiplication. | Peipei Zhou, Hyunseok Park, Zhenman Fang, Jason Cong, Andr DeHon |
| 2016 | FPGA | Pitfalls and Tradeoffs in Simultaneous, On-Chip FPGA Delay Measurement. | Timothy A. Linscott, Benjamin Gojman, Raphael Rubin, Andr DeHon |
| 2015 | ASPLOS | Architectural Support for Software-Defined Metadata Processing. | Udit Dhawan, Catalin Hritcu, Raphael Rubin, Nikos Vasilakis, Silviu Chiricescu, Jonathan M. Smith, Thomas F. Knight Jr., Benjamin C. Pierce, Andr DeHon |
| 2015 | FPGA | Impact of Memory Architecture on FPGA Energy Consumption. | Edin Kadric, David Lakata, Andr DeHon |
| 2014 | FCCM | GROK-INT: Generating Real On-Chip Knowledge for Interconnect Delays Using Timing Extraction. | Benjamin Gojman, Andr DeHon |
| 2014 | FCCM | Kung Fu Data Energy - Minimizing Communication Energy in FPGA Computations. | Edin Kadric, Kunal Mahajan, Andr DeHon |
| 2014 | FCCM | Energy Reduction through Differential Reliability and Lightweight Checking. | Edin Kadric, Kunal Mahajan, Andr DeHon |
| 2014 | FPGA | Wordwidth, instructions, looping, and virtualization: the role of sharing in absolute energy minimization. | Andr DeHon |
| 2014 | ISCA | PUMP: a programmable unit for metadata processing. | Udit Dhawan, Nikos Vasilakis, Raphael Rubin, Silviu Chiricescu, Jonathan M. Smith, Thomas F. Knight Jr., Benjamin C. Pierce, Andr DeHon |
| 2014 | POPL | A verified information-flow architecture. | Arthur Azevedo de Amorim, Nathan Collins, Andr DeHon, Delphine Demange, Catalin Hritcu, David Pichardie, Benjamin C. Pierce, Randy Pollack, Andrew Tolmach |
| 2013 | ARITH | Accurate Parallel Floating-Point Accumulation. | Edin Kadric, Paul Gurniak, Andr DeHon |
| 2013 | CCS | Low-fat pointers: compact encoding and efficient gate-level implementation of fat pointers for spatial safety and capability-based security. | Albert Kwon, Udit Dhawan, Jonathan M. Smith, Thomas F. Knight Jr., Andr DeHon |
| 2013 | FPGA | Location, location, location: the role of spatial locality in asymptotic energy minimization. | Andr DeHon |
| 2013 | FPGA | Area-efficient near-associative memories on FPGAs. | Udit Dhawan, Andr DeHon |
| 2013 | FPGA | GROK-LAB: generating real on-chip knowledge for intra-cluster delays using timing extraction. | Benjamin Gojman, Sirisha Nalmela, Nikil Mehta, Nicholas Howarth, Andr DeHon |
| 2012 | FPGA | Limit study of energy & delay benefits of component-specific routing. | Nikil Mehta, Raphael Rubin, Andr DeHon |
| 2011 | FPGA | Timing-driven pathfinder pathology and remediation: quantifying and reducing delay noise in VPR-pathfinder. | Raphael Rubin, Andr DeHon |
| 2011 | SOSP | Preliminary design of the SAFE platform. | Andr DeHon, Ben Karel, Thomas F. Knight Jr., Gregory Malecha, Benot Montagu, Robin Morisset, Greg Morrisett, Benjamin C. Pierce, Randy Pollack, Sumit Ray, Olin Shivers, Jonathan M. Smith, Gregory Sullivan |
| 2010 | DATE | Vision for cross-layer optimization to address the dual challenges of energy and reliability. | Andr DeHon, Heather M. Quinn, Nicholas P. Carter |
| 2009 | FCCM | Accelerating SPICE Model-Evaluation using FPGAs. | Nachiket Kapre, Andr DeHon |
| 2009 | FPGA | CMOS vs Nano: comrades or rivals? | Deming Chen, Russell Tessier, Kaustav Banerjee, Mojy C. Chian, Andr DeHon, Shinobu Fujita, James Hutchby, Steve Trimberger |
| 2009 | FPGA | Choose-your-own-adventure routing: lightweight load-time defect avoidance. | Raphael Rubin, Andr DeHon |
| 2009 | FPL | Performance comparison of single-precision SPICE Model-Evaluation on FPGA, GPU, Cell, and multi-core processors. | Nachiket Kapre, Andr DeHon |
| 2007 | ARITH | Optimistic Parallelization of Floating-Point Accumulation. | Nachiket Kapre, Andr DeHon |
| 2006 | ASPDAC | SAT-based optimal hypergraph partitioning with replication. | Michael G. Wrighton, Andr DeHon |
| 2006 | FCCM | GraphStep: A System Architecture for Sparse-Graph Algorithms. | Michael DeLorimier, Nachiket Kapre, Nikil Mehta, Dominic Rizzo, Ian Eslick, Raphael Rubin, Toms E. Uribe, Thomas F. Knight Jr., Andr DeHon |
| 2006 | FCCM | Packet Switched vs. Time Multiplexed FPGA Overlay Networks. | Nachiket Kapre, Nikil Mehta, Michael DeLorimier, Raphael Rubin, Henry Barnor, Michael J. Wilson, Michael G. Wrighton, Andr DeHon |
| 2005 | FPGA | Design of programmable interconnect for sublithographic programmable logic arrays. | Andr DeHon |
| 2005 | FPGA | Floating-point sparse matrix-vector multiply for FPGAs. | Michael DeLorimier, Andr DeHon |
| 2005 | ICCAD | Hybrid CMOS/nanoelectronic digital circuits: devices, architectures, and design automation. | Andr DeHon, Konstantin Likharev |
| 2004 | FCCM | Design Patterns for Reconfigurable Computing. | Andr DeHon, Joshua Adams, Michael DeLorimier, Nachiket Kapre, Yuki Matsuda, Helia Naeimi, Michael C. Vanier, Michael G. Wrighton |
| 2004 | FPGA | What is the right model for programming and using modern FPGAs? | Andr DeHon, Brad L. Hutchings, Daryl Rudusky, James Hwang, Nikhil, Salil Raje, Adrian Stoica |
| 2004 | FPGA | Nanowire-based sublithographic programmable logic arrays. | Andr DeHon, Michael J. Wilson |
| 2003 | FPGA | Stochastic, spatial routing for hypergraphs, trees, and meshes. | Randy Huang, John Wawrzynek, Andr DeHon |
| 2003 | FPGA | Design of FPGA interconnect for multilevel metalization. | Raphael Rubin, Andr DeHon |
| 2003 | FPGA | Hardware-assisted simulated annealing with application for fast FPGA placement. | Michael G. Wrighton, Andr DeHon |
| 2002 | FCCM | Hardware-Assisted Fast Routing. | Andr DeHon, Randy Huang, John Wawrzynek |
| 2002 | FPGA | Analysis of quasi-static scheduling techniques in a virtualized reconfigurable machine. | Yury Markovsky, Eylon Caspi, Randy Huang, Joseph Yeh, Michael Chu, John Wawrzynek, Andr DeHon |
| 2002 | ICCAD | Molecular electronics: devices, systems and tools for gigagate, gigabit chips. | Michael Butts, Andr DeHon, Seth Copen Goldstein |
| 2000 | FPL | Stream Computations Organized for Reconfigurable Execution (SCORE). | Eylon Caspi, Michael Chu, Randy Huang, Joseph Yeh, John Wawrzynek, Andr DeHon |
| 2000 | SPAA | Compact, multilayer layout for butterfly fat-tree. | Andr DeHon |
| 1999 | DAC | Reconfigurable Computing: What, Why, and Implications for Design Automation. | Andr DeHon, John Wawrzynek |
| 1999 | FPGA | Balancing Interconnect and Computation in a Reconfiguable Computing Array (or, why you don't really want 100% LUT utilization). | Andr DeHon |
| 1999 | FPGA | HSRA: High-Speed, Hierarchical Synchroous Reconfigurable Array. | William Tsu, Kip Macy, Atul Joshi, Randy Huang, Norman Walker, Tony Tung, Omid Rowhani, George Varghese, John Wawrzynek, Andr DeHon |
| 1998 | FCCM | Object Oriented Circuit-Generators in Java. | Michael Chu, Nicholas Weaver, Kolja Sulimma, Andr DeHon, John Wawrzynek |
| 1998 | FPGA | Fast Module Mapping and Placement for Datapaths in FPGAs. | Timothy J. Callahan, Philip Chong, Andr DeHon, John Wawrzynek |
| 1996 | FCCM | MATRIX: a reconfigurable computing architecture with configurable instruction distribution and deployable resources. | Ethan Mirsky, Andr DeHon |
| 1996 | FPGA | Entropy, Counting, and Programmable Interconnect. | Andr DeHon |
| 1996 | FPGA | DPGA Utilization and Application. | Andr DeHon |
| 1994 | ISCA | METRO: A Router Architecture for High-Performance, Short-Haul Routing Networks. | Frederic T. Chong, Henry Minsky, Andr DeHon, Matthew E. Becker, Samuel Peretz, Eran Egozy, Thomas F. Knight Jr. |
| 1994 | ITC | In-System Timing Extraction and Control Through Scan-Based, Test-Access Ports. | Andr DeHon |