| 2026 | ASPLOS | Graphiti: Formally Verified Out-of-Order Execution in Dataflow Circuits. | Yann Herklotz, Ayatallah Elakhras, Martina Camaioni, Paolo Ienne, Lana Josipovic, Thomas Bourgeat |
| 2026 | FCCM | NetCilk: Extending Task-Level Parallelism Seamlessly across FPGAs. | Mohamed Shahawy, Canberk Snmez, Paolo Ienne |
| 2026 | FPGA | Out with LSQs: Custom Circuits for Memory Access Reordering in Dynamic HLS. | Rouzbeh Pirayadi, Ayatallah Elakhras, Mirjana Stojilovic, Paolo Ienne |
| 2026 | FPGA | Chext: A Domain-specific Language for Safe and Agile Elastic Dataflow Accelerators. | Canberk Snmez, Mohamed Shahawy, Paolo Ienne |
| 2025 | ASPLOS | ElasticMiter: Formally Verified Dataflow Circuit Rewrites. | Ayatallah Elakhras, Jiahui Xu, Martin Erhart, Paolo Ienne, Lana Josipovic |
| 2025 | FCCM | DRSA: Accelerating Macro Placement on Commercial FPGAs. | Menzo Bouaissi, Paolo Ienne, Lana Josipovic, Andrea Guerrieri |
| 2025 | FCCM | HBMex: An Attachment for Nonbursting Accelerators to Enhance HBM Performance. | Canberk Snmez, Mohamed Shahawy, Paolo Ienne |
| 2025 | FPGA | FRIDA: Reconfigurable Arrays for Dynamically Scheduled High-Level Synthesis. | Louis Coulon, Lucas Ramirez, Jason Helge Anderson, Mirjana Stojilovic, Paolo Ienne |
| 2025 | FPL | Compile in Seconds and Run on an FPGA with DynaRapid. | Andrea Guerrieri, Isaac John Wetenkamp, Chris Lavin, Eddie Hung, Lana Josipovic, Paolo Ienne |
| 2025 | ICCAD | FRESCO: Efficient Subgraph Enumeration for Scalable Clustering in Heterogeneous CGRAs. | Louis Coulon, Adham Ragab, Jason Anderson, Mirjana Stojilovic, Paolo Ienne |
| 2024 | FCCM | HardCilk: Cilk-like Task Parallelism for FPGAs. | Mohamed Shahawy, Canberk Snmez, Cemalettin Belentepe, Paolo Ienne |
| 2024 | FPGA | Survival of the Fastest: Enabling More Out-of-Order Execution in Dataflow Circuits. | Ayatallah Elakhras, Andrea Guerrieri, Lana Josipovic, Paolo Ienne |
| 2024 | FPGA | DynaRapid: From C to FPGA in a Few Seconds. | Andrea Guerrieri, Srijeet Guha, Lana Josipovic, Paolo Ienne |
| 2024 | FPL | DynaRapid: Fast-Tracking from C to Routed Circuits. | Andrea Guerrieri, Srijeet Guha, Chris Lavin, Eddie Hung, Lana Josipovic, Paolo Ienne |
| 2024 | FPL | FlexiMem: Flexible Shared Virtual Memory for PCIe-attached FPGAs. | Canberk Snmez, Mohamed Shahawy, Cemalettin Cem Belentepe, Paolo Ienne |
| 2023 | FPGA | Straight to the Queue: Fast Load-Store Queue Allocation in Dataflow Circuits. | Ayatallah Elakhras, Riya Sawhney, Andrea Guerrieri, Lana Josipovic, Paolo Ienne |
| 2023 | FPGA | Regularity Matters: Designing Practical FPGA Switch-Blocks. | Stefan Nikolic, Paolo Ienne |
| 2022 | FCCM | Resource Sharing in Dataflow Circuits. | Lana Josipovic, Axel Marmet, Andrea Guerrieri, Paolo Ienne |
| 2022 | FPL | Unleashing Parallelism in Elastic Circuits with Faster Token Delivery. | Ayatallah Elakhras, Andrea Guerrieri, Lana Josipovic, Paolo Ienne |
| 2022 | FPL | A Comprehensive Timing Model for Accurate Frequency Tuning in Dataflow Circuits. | Carmine Rizzi, Andrea Guerrieri, Paolo Ienne, Lana Josipovic |
| 2022 | SPAA | Scalable Fine-Grained Parallel Cycle Enumeration Algorithms. | Jovan Blanusa, Paolo Ienne, Kubilay Atasu |
| 2021 | FPGA | Resource Sharing in Dataflow Circuits. | Lana Josipovic, Axel Marmet, Andrea Guerrieri, Paolo Ienne |
| 2021 | FPGA | Global Is the New Local: FPGA Architecture at 5nm and Beyond. | Stefan Nikolic, Francky Catthoor, Zsolt Tokei, Paolo Ienne |
| 2021 | FPL | Turning PathFinder Upside-Down: Exploring FPGA Switch-Blocks by Negotiating Switch Presence. | Stefan Nikolic, Paolo Ienne |
| 2021 | ISCA | Large-Scale Graph Processing on FPGAs with Caches for Thousands of Simultaneous Misses. | Mikhail Asiatici, Paolo Ienne |
| 2020 | FPGA | Combining Dynamic & Static Scheduling in High-level Synthesis. | Jianyi Cheng, Lana Josipovic, George A. Constantinides, Paolo Ienne, John Wickerson |
| 2020 | FPGA | Invited Tutorial: Dynamatic: From C/C++ to Dynamically Scheduled Circuits. | Lana Josipovic, Andrea Guerrieri, Paolo Ienne |
| 2020 | FPGA | Buffer Placement and Sizing for High-Performance Dataflow Circuits. | Lana Josipovic, Shabnam Sheikhha, Andrea Guerrieri, Paolo Ienne, Jordi Cortadella |
| 2020 | FPGA | Straight to the Point: Intra- and Intercluster LUT Connections to Mitigate the Delay of Programmable Routing. | Stefan Nikolic, Grace Zgheib, Paolo Ienne |
| 2020 | FPL | Timing-Driven Placement for FPGA Architectures with Dedicated Routing Paths. | Stefan Nikolic, Grace Zgheib, Paolo Ienne |
| 2019 | FPGA | Stop Crying Over Your Cache Miss Rate: Handling Efficiently Thousands of Outstanding Misses in FPGAs. | Mikhail Asiatici, Paolo Ienne |
| 2019 | FPGA | Speculative Dataflow Circuits. | Lana Josipovic, Andrea Guerrieri, Paolo Ienne |
| 2019 | FPGA | On Feasibility of FPGAs Without Dedicated Programmable Interconnect Structure. | Anastasiia Kucherenko, Stefan Nikolic, Paolo Ienne |
| 2019 | FPL | DynaBurst: Dynamically Assemblying DRAM Bursts over a Multitude of Random Accesses. | Mikhail Asiatici, Paolo Ienne |
| 2019 | FPL | Finding a Needle in the Haystack of Hardened Interconnect Patterns. | Stefan Nikolic, Grace Zgheib, Paolo Ienne |
| 2018 | FPGA | FPGAs in the Datacenters: the Case of Parallel Hybrid Super Scalar String Sample Sort (pHS | Mikhail Asiatici, Damian Maiorano, Paolo Ienne |
| 2018 | FPGA | LEOSoC: An Open-Source Cross-Platform Embedded Linux Library for Managing Hardware Accelerators in Heterogeneous System-on-Chips(Abstract Only). | Andrea Guerrieri, Sahand Kashani-Akhavan, Mikhail Asiatici, Pasquale Lombardi, Bilel Belhadj, Paolo Ienne |
| 2018 | FPGA | Dynamically Scheduled High-level Synthesis. | Lana Josipovic, Radhika Ghosal, Paolo Ienne |
| 2018 | SBAC-PAD | Exploiting Compute Caches for Memory Bound Vector Operations. | Joo Vieira, Nuno Roma, Pedro Toms, Paolo Ienne, Gabriel Falco Paiva Fernandes |
| 2017 | ACSSC | From C to elastic circuits. | Lana Josipovic, Philip Brisk, Paolo Ienne |
| 2017 | DAC | Arbitrary Precision and Complexity Tradeoffs for Gate-Level Information Flow Tracking. | Andrew Becker, Wei Hu, Yu Tai, Philip Brisk, Ryan Kastner, Paolo Ienne |
| 2017 | FCCM | An Out-of-Order Load-Store Queue for Spatial Computing. | Lana Josipovic, Philip Brisk, Paolo Ienne |
| 2017 | FPGA | NAND-NOR: A Compact, Fast, and Delay Balanced FPGA Logic Element. | Zhihong Huang, Xing Wei, Grace Zgheib, Wei Li, Yu Lin, Zhenghong Jiang, Kaihui Tu, Paolo Ienne, Haigang Yang |
| 2017 | FPL | Evaluating FPGA clusters under wide ranges of design parameters. | Grace Zgheib, Paolo Ienne |
| 2016 | DATE | Instruction Set Extensions for secure applications. | Francesco Regazzoni, Paolo Ienne |
| 2016 | FPGA | FPRESSO: Enabling Express Transistor-Level Exploration of FPGA Architectures. | Grace Zgheib, Manana Lortkipanidze, Muhsen Owaida, David Novo, Paolo Ienne |
| 2016 | FPL | Designing a virtual runtime for FPGA accelerators in the cloud. | Mikhail Asiatici, Nithin George, Kizheppatt Vipin, Suhaib A. Fahmy, Paolo Ienne |
| 2016 | FPL | Preface. | Paolo Ienne, Walid A. Najjar, Jason Helge Anderson, Philip Brisk, Walter Stechele |
| 2016 | FPL | Fast hierarchical NPN classification. | Ana Petkovska, Mathias Soeken, Giovanni De Micheli, Paolo Ienne, Alan Mishchenko |
| 2016 | ICCAD | Imprecise security: quality and complexity tradeoffs for hardware information flow tracking. | Wei Hu, Andrew Becker, Armita Ardeshiricham, Yu Tai, Paolo Ienne, Dejun Mu, Ryan Kastner |
| 2016 | ICCAD | Fast generation of lexicographic satisfiable assignments: enabling canonicity in SAT-based applications. | Ana Petkovska, Alan Mishchenko, Mathias Soeken, Giovanni De Micheli, Robert K. Brayton, Paolo Ienne |
| 2016 | SAT | Heuristic NPN Classification for Large Functions Using AIGs and LEXSAT. | Mathias Soeken, Alan Mishchenko, Ana Petkovska, Baruch Sterin, Paolo Ienne, Robert K. Brayton, Giovanni De Micheli |
| 2015 | DATE | Retraining-based timing error mitigation for hardware neural networks. | Jiachao Deng, Yuntan Fang, Zidong Du, Ying Wang, Huawei Li, Olivier Temam, Paolo Ienne, David Novo, Xiaowei Li, Yunji Chen, Chengyong Wu |
| 2015 | FCCM | Fast Design Space Exploration Using Vivado HLS: Non-binary LDPC Decoders. | Joo Andrade, Nithin George, Kimon Karras, David Novo, Vtor Manuel Mendes da Silva, Paolo Ienne, Gabriel Falco Paiva Fernandes |
| 2015 | FPL | From low-architectural expertise up to high-throughput non-binary LDPC decoders: Optimization guidelines using high-level synthesis. | Joo Andrade, Nithin George, Kimon Karras, David Novo, Vtor Manuel Mendes da Silva, Paolo Ienne, Gabriel Falco Paiva Fernandes |
| 2015 | FPL | Automatic support for multi-module parallelism from computational patterns. | Nithin George, HyoukJoong Lee, David Novo, Muhsen Owaida, David Andrews, Kunle Olukotun, Paolo Ienne |
| 2015 | FPL | A technology mapper for depth-constrained FPGA logic cells. | Zhenghong Jiang, Grace Zgheib, Colin Yu Lin, David Novo, Zhihong Huang, Liqun Yang, Haigang Yang, Paolo Ienne |
| 2015 | ISCA | ShiDianNao: shifting vision processing closer to the sensor. | Zidong Du, Robert Fasthuber, Tianshi Chen, Paolo Ienne, Ling Li, Tao Luo, Xiaobing Feng, Yunji Chen, Olivier Temam |
| 2014 | CASES | A low-cost memory interface for high-throughput accelerators. | Jing Huang, Yuanjie Huang, Olivier Temam, Paolo Ienne, Yunji Chen, Chengyong Wu |
| 2014 | DATE | SKETCHILOG: Sketching combinational circuits. | Andrew Becker, David Novo, Paolo Ienne |
| 2014 | DATE | Energy efficient MIMO processing: A case study of opportunistic run-time approximations. | David Novo, Nazanin Farahpour, Paolo Ienne, Ubaid Ahmad, Francky Catthoor |
| 2014 | FAST | Wear unleveling: improving NAND flash lifetime by balancing page endurance. | Xavier Jimenez, David Novo, Paolo Ienne |
| 2014 | FPGA | Revisiting and-inverter cones. | Grace Zgheib, Liqun Yang, Zhihong Huang, David Novo, Hadi Parandeh-Afshar, Haigang Yang, Paolo Ienne |
| 2014 | FPL | Hardware system synthesis from Domain-Specific Languages. | Nithin George, HyoukJoong Lee, David Novo, Tiark Rompf, Kevin J. Brown, Arvind K. Sujeeth, Martin Odersky, Kunle Olukotun, Paolo Ienne |
| 2014 | ICCAD | Constrained interpolation for guided logic synthesis. | Ana Petkovska, David Novo, Alan Mishchenko, Paolo Ienne |
| 2013 | ACSSC | Automated circuit elaboration from incomplete architectural descriptions. | Andrew Becker, David Novo, Paolo Ienne |
| 2013 | CHES | Sleuth: Automated Verification of Software Power Analysis Countermeasures. | Ali Galip Bayrak, Francesco Regazzoni, David Novo, Paolo Ienne |
| 2013 | DATE | An EDA-friendly protection scheme against side-channel attacks. | Ali Galip Bayrak, Nikola Velickovic, Francesco Regazzoni, David Novo, Philip Brisk, Paolo Ienne |
| 2013 | DATE | Fast and accurate BER estimation methodology for I/O links based on extreme value theory. | Alessandro Cevrero, Nestor E. Evmorfopoulos, Charalampos Antoniadis, Paolo Ienne, Yusuf Leblebici, Andreas Burg, Georgios I. Stamoulis |
| 2013 | DATE | Phœnix: reviving MLC blocks as SLC to extend NAND flash devices lifetime. | Xavier Jimenez, David Novo, Paolo Ienne |
| 2013 | DATE | Accuracy vs speed tradeoffs in the estimation of fixed-point errors on linear time-invariant systems. | David Novo, Sara El Alaoui, Paolo Ienne |
| 2013 | FCCM | A Case for Heterogeneous Technology-Mapping: Soft Versus Hard Multiplexers. | Madhura Purnaprajna, Paolo Ienne |
| 2013 | FPGA | Elastic CGRAs. | Yuanjie Huang, Paolo Ienne, Olivier Temam, Yunji Chen, Chengyong Wu |
| 2013 | FPGA | Shadow AICs: reaping the benefits of and-inverter cones with minimal architectural impact (abstract only). | Hadi Parandeh-Afshar, Grace Zgheib, David Novo, Madhura Purnaprajna, Paolo Ienne |
| 2013 | FPL | Shadow And-Inverter Cones. | Hadi Parandeh-Afshar, Grace Zgheib, David Novo, Madhura Purnaprajna, Paolo Ienne |
| 2012 | DAC | Software controlled cell bit-density to improve NAND flash lifetime. | Xavier Jimenez, David Novo, Paolo Ienne |
| 2012 | DATE | Selective flexibility: Breaking the rigidity of datapath merging. | Mirjana Stojilovic, David Novo, Lazar Saranovac, Philip Brisk, Paolo Ienne |
| 2012 | EuroPar | CRAW/P: A Workload Partition Method for the Efficient Parallel Simulation of Manycores. | Shuai Jiao, Paolo Ienne, Xiaochun Ye, Da Wang, Dongrui Fan, Ninghui Sun |
| 2012 | FCCM | Shortening Design Time through Multiplatform Simulations with a Portable OpenCL Golden-model: The LDPC Decoder Case. | Gabriel Falco, Muhsen Owaida, David Novo, Madhura Purnaprajna, Nikolaos Bellas, Christos D. Antonopoulos, Georgios Karakonstantis, Andreas Burg, Paolo Ienne |
| 2012 | FPGA | Reducing the cost of floating-point mantissa alignment and normalization in FPGAs. | Yehdhih Ould Mohammed Moctar, Nithin George, Hadi Parandeh-Afshar, Paolo Ienne, Guy G. F. Lemieux, Philip Brisk |
| 2012 | FPGA | Rethinking FPGAs: elude the flexibility excess of LUTs with and-inverter cones. | Hadi Parandeh-Afshar, Hind Benbihi, David Novo, Paolo Ienne |
| 2011 | DAC | A first step towards automatic application of power analysis countermeasures. | Ali Galip Bayrak, Francesco Regazzoni, Philip Brisk, Franois-Xavier Standaert, Paolo Ienne |
| 2011 | DAC | Power-gated MOS current mode logic (PG-MCML): a power aware DPA-resistant standard cell library. | Alessandro Cevrero, Francesco Regazzoni, Micheal Schwander, Stphane Badel, Paolo Ienne, Yusuf Leblebici |
| 2011 | FPGA | Reducing the pressure on routing resources of FPGAs with generic logic chains. | Hadi Parandeh-Afshar, Grace Zgheib, Philip Brisk, Paolo Ienne |
| 2011 | FPL | Measuring and Reducing the Performance Gap between Embedded and Soft Multipliers on FPGAs. | Hadi Parandeh-Afshar, Paolo Ienne |
| 2010 | ASPDAC | A high-level synthesis flow for custom instruction set extensions for application-specific processors. | Nagaraju Pothineni, Philip Brisk, Paolo Ienne, Anshul Kumar, Kolin Paul |
| 2010 | FCCM | Highly Versatile DSP Blocks for Improved FPGA Arithmetic Performance. | Hadi Parandeh-Afshar, Paolo Ienne |
| 2010 | FPL | Synthesis of Floating-Point Addition Clusters on FPGAs Using Carry-Save Arithmetic. | Amit Verma, Ajay Kumar Verma, Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne |
| 2009 | ARITH | Challenges in Automatic Optimization of Arithmetic Circuits. | Ajay Kumar Verma, Philip Brisk, Paolo Ienne |
| 2009 | ASPDAC | Hybrid LZA: a near optimal implementation of the leading zero anticipator. | Amit Verma, Ajay Kumar Verma, Philip Brisk, Paolo Ienne |
| 2009 | CHES | A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions. | Francesco Regazzoni, Alessandro Cevrero, Franois-Xavier Standaert, Stphane Badel, Theo Kluter, Philip Brisk, Yusuf Leblebici, Paolo Ienne |
| 2009 | DAC | Way Stealing: cache-assisted automatic instruction set extensions. | Theo Kluter, Philip Brisk, Paolo Ienne, Edoardo Charbon |
| 2009 | FCCM | FPGA Implementation of a Single-Precision Floating-Point Multiply-Accumulator with Single-Cycle Accumulation. | Arun Paidimarri, Alessandro Cevrero, Philip Brisk, Paolo Ienne |
| 2009 | FPGA | 3D configuration caching for 2D FPGAs. | Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Philip Brisk, Yusuf Leblebici, Paolo Ienne, Maurizio Skerlj |
| 2009 | FPL | Using 3D integration technology to realize multi-context FPGAs. | Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Maurizio Skerlj, Philip Brisk, Yusuf Leblebici, Paolo Ienne |
| 2009 | FPL | Exploiting fast carry-chains of FPGAs for designing compressor trees. | Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne |
| 2009 | ICCAD | Memory organization and data layout for instruction set extensions with architecturally visible storage. | Panagiotis Athanasopoulos, Philip Brisk, Yusuf Leblebici, Paolo Ienne |
| 2009 | ICCAD | Iterative layering: Optimizing arithmetic circuits by structuring the information flow. | Ajay Kumar Verma, Philip Brisk, Paolo Ienne |
| 2008 | ASPDAC | Efficient synthesis of compressor trees on FPGAs. | Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne |
| 2008 | ASPDAC | Fast, quasi-optimal, and pipelined instruction-set extensions. | Ajay Kumar Verma, Philip Brisk, Paolo Ienne |
| 2008 | CASES | Design space exploration for field programmable compressor trees. | Seyed-Hosein Attarzadeh-Niaki, Alessandro Cevrero, Philip Brisk, Chrysostomos Nicopoulos, Frank K. Grkaynak, Yusuf Leblebici, Paolo Ienne |
| 2008 | DATE | Improving Synthesis of Compressor Trees on FPGAs via Integer Linear Programming. | Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne |
| 2008 | DATE | Variable Latency Speculative Addition: A New Paradigm for Arithmetic Circuit Design. | Ajay Kumar Verma, Philip Brisk, Paolo Ienne |
| 2008 | FPGA | Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs. | Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay Kumar Verma, Philip Brisk, Frank K. Grkaynak, Yusuf Leblebici, Paolo Ienne |
| 2008 | FPGA | A novel FPGA logic block for improved arithmetic performance. | Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne |
| 2007 | ASPDAC | Improving XOR-Dominated Circuits by Exploiting Dependencies between Operands. | Ajay Kumar Verma, Paolo Ienne |
| 2007 | CASES | An optimistic and conservative register assignment heuristic for chordal graphs. | Philip Brisk, Ajay Kumar Verma, Paolo Ienne |
| 2007 | CASES | Rethinking custom ISE identification: a new processor-agnostic method. | Ajay Kumar Verma, Philip Brisk, Paolo Ienne |
| 2007 | DAC | Enhancing FPGA Performance for Arithmetic Circuits. | Philip Brisk, Ajay Kumar Verma, Paolo Ienne, Hadi Parandeh-Afshar |
| 2007 | DAC | Progressive Decomposition: A Heuristic to Structure Arithmetic Circuits. | Ajay Kumar Verma, Philip Brisk, Paolo Ienne |
| 2007 | DATE | Automatic synthesis of compressor trees: reevaluating large counters. | Ajay Kumar Verma, Paolo Ienne |
| 2007 | ICCAD | Optimal polynomial-time interprocedural register allocation for high-level synthesis and ASIP design. | Philip Brisk, Ajay Kumar Verma, Paolo Ienne |
| 2006 | DAC | Towards the automatic exploration of arithmetic-circuit architectures. | Ajay Kumar Verma, Paolo Ienne |
| 2006 | DATE | Automatic identification of application-specific functional units with architecturally visible storage. | Partha Biswas, Nikil D. Dutt, Paolo Ienne, Laura Pozzi |
| 2006 | DATE | Combining algorithm exploration with instruction set design: a case study in elliptic curve cryptography. | Johann Groschdl, Paolo Ienne, Laura Pozzi, Stefan Tillich, Ajay Kumar Verma |
| 2006 | IOLTS | Designing Robust Checkers in the Presence of Massive Timing Errors. | Frederic Worm, Patrick Thiran, Paolo Ienne |
| 2006 | VLSID | Performance and Energy Benefits of Instruction Set Extensions in an FPGA Soft Core. | Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Paolo Ienne, Laura Pozzi |
| 2005 | CASES | Exploiting pipelining to relax register-file port constraints of instruction-set extensions. | Laura Pozzi, Paolo Ienne |
| 2005 | DATE | ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement. | Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Laura Pozzi, Paolo Ienne |
| 2005 | ISCAS | Quantitative modelling and comparison of communication schemes to guarantee quality-of-service in networks-on-chip. | Mehmet Derin Harmanci, Nuria Pazos Escudero, Yusuf Leblebici, Paolo Ienne |
| 2005 | ISCAS | Self-calibrating networks-on-chip. | Frederic Worm, Paolo Ienne, Patrick Thiran, Giovanni De Micheli |
| 2004 | DAC | Introduction of local memory elements in instruction set extensions. | Partha Biswas, Vinay Choudhary, Kubilay Atasu, Laura Pozzi, Paolo Ienne, Nikil D. Dutt |
| 2004 | DAC | Virtual memory window for application-specific reconfigurable coprocessors. | Miljan Vuletic, Laura Pozzi, Paolo Ienne |
| 2004 | DATE | Operating System Support for Interface Virtualisation of Reconfigurable Coprocessors. | Miljan Vuletic, Ludovic Righetti, Laura Pozzi, Paolo Ienne |
| 2004 | FCCM | Virtual Memory Window for a Portable Reconfigurable Cryptography Coprocessor. | Miljan Vuletic, Laura Pozzi, Paolo Ienne |
| 2004 | FPL | Dynamic Prefetching in the Virtual Memory Window of Portable Reconfigurable Coprocessors. | Miljan Vuletic, Laura Pozzi, Paolo Ienne |
| 2004 | ICCAD | Improved use of the carry-save representation for the synthesis of complex arithmetic circuits. | Ajay Kumar Verma, Paolo Ienne |
| 2004 | ICCAD | Soft self-synchronising codes for self-calibrating communication. | Frederic Worm, Paolo Ienne, Patrick Thiran |
| 2004 | SCOPES | Automatically Customising VLIW Architectures with Coarse Grained Application-Specific Functional Units. | Diviya Jain, Anshul Kumar, Laura Pozzi, Paolo Ienne |
| 2003 | DAC | Automatic application-specific instruction-set extensions under microarchitectural constraints. | Kubilay Atasu, Laura Pozzi, Paolo Ienne |
| 2002 | DATE | Automatic Topology-Based Identification of Instruction-Set Extensions for Embedded Processors. | Laura Pozzi, Miljan Vuletic, Paolo Ienne |
| 1998 | DAC | Practical Experiences with Standard-Cell Based Datapath Design Tools: Do We Really Need Regular Layouts? | Paolo Ienne, Alexander Grieing |
| 1997 | IWANN | Digital Connectionist Hardware: Current Problems and Future Challenges. | Paolo Ienne |