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3D configuration caching for 2D FPGAs.

Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Philip Brisk, Yusuf Leblebici, Paolo Ienne, Maurizio Skerlj

VenueAFPGA
Year2009
ProceedingsFPGA
DBLP recordconf/fpga/CevreroAPBLIS09 ↗

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