Hadi Parandeh-Afshar
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
20
Venues
7
Active years
2006–2018
Best venue rank
A*
Where they publish
Papers
20 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2018 | ASPDAC | Exploration of approximate multipliers design space using carry propagation free compressors. | Sina Boroumand, Hadi Parandeh-Afshar, Philip Brisk, Siamak Mohammadi |
| 2018 | DATE | Approximate quaternary addition with the fast carry chains of FPGAs. | Sina Boroumand, Hadi Parandeh-Afshar, Philip Brisk |
| 2014 | FPGA | Revisiting and-inverter cones. | Grace Zgheib, Liqun Yang, Zhihong Huang, David Novo, Hadi Parandeh-Afshar, Haigang Yang, Paolo Ienne |
| 2013 | FPGA | Shadow AICs: reaping the benefits of and-inverter cones with minimal architectural impact (abstract only). | Hadi Parandeh-Afshar, Grace Zgheib, David Novo, Madhura Purnaprajna, Paolo Ienne |
| 2013 | FPL | Shadow And-Inverter Cones. | Hadi Parandeh-Afshar, Grace Zgheib, David Novo, Madhura Purnaprajna, Paolo Ienne |
| 2012 | FPGA | Reducing the cost of floating-point mantissa alignment and normalization in FPGAs. | Yehdhih Ould Mohammed Moctar, Nithin George, Hadi Parandeh-Afshar, Paolo Ienne, Guy G. F. Lemieux, Philip Brisk |
| 2012 | FPGA | Rethinking FPGAs: elude the flexibility excess of LUTs with and-inverter cones. | Hadi Parandeh-Afshar, Hind Benbihi, David Novo, Paolo Ienne |
| 2011 | FPGA | Reducing the pressure on routing resources of FPGAs with generic logic chains. | Hadi Parandeh-Afshar, Grace Zgheib, Philip Brisk, Paolo Ienne |
| 2011 | FPL | Measuring and Reducing the Performance Gap between Embedded and Soft Multipliers on FPGAs. | Hadi Parandeh-Afshar, Paolo Ienne |
| 2010 | FCCM | Highly Versatile DSP Blocks for Improved FPGA Arithmetic Performance. | Hadi Parandeh-Afshar, Paolo Ienne |
| 2010 | FPL | Synthesis of Floating-Point Addition Clusters on FPGAs Using Carry-Save Arithmetic. | Amit Verma, Ajay Kumar Verma, Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne |
| 2009 | FPGA | 3D configuration caching for 2D FPGAs. | Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Philip Brisk, Yusuf Leblebici, Paolo Ienne, Maurizio Skerlj |
| 2009 | FPL | Using 3D integration technology to realize multi-context FPGAs. | Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Maurizio Skerlj, Philip Brisk, Yusuf Leblebici, Paolo Ienne |
| 2009 | FPL | Exploiting fast carry-chains of FPGAs for designing compressor trees. | Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne |
| 2008 | ASPDAC | Efficient synthesis of compressor trees on FPGAs. | Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne |
| 2008 | DATE | Improving Synthesis of Compressor Trees on FPGAs via Integer Linear Programming. | Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne |
| 2008 | FPGA | Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs. | Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay Kumar Verma, Philip Brisk, Frank K. Grkaynak, Yusuf Leblebici, Paolo Ienne |
| 2008 | FPGA | A novel FPGA logic block for improved arithmetic performance. | Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne |
| 2007 | DAC | Enhancing FPGA Performance for Arithmetic Circuits. | Philip Brisk, Ajay Kumar Verma, Paolo Ienne, Hadi Parandeh-Afshar |
| 2006 | ISCAS | A very high performance address BUS encoder. | Hadi Parandeh-Afshar, Ali Afzali-Kusha, Ali Khaki-Firooz |