| 2023 | CGO | Compiling Functions onto Digital Microfluidics. | Tyson Loveless, Philip Brisk |
| 2023 | FCCM | Feature Extraction Accelerator for Streaming Time Series. | Prithviraj Yuvaraj, Amin Akalantar, Eamonn J. Keogh, Philip Brisk |
| 2021 | FCCM | FA-LAMP: FPGA-Accelerated Learned Approximate Matrix Profile for Time Series Similarity Prediction. | Amin Kalantar, Zachary Zimmerman, Philip Brisk |
| 2020 | CGO | A performance-optimizing compiler for cyber-physical digital microfluidic biochips. | Tyson Loveless, Jason Ott, Philip Brisk |
| 2020 | SC | Tuning floating-point precision using dynamic program information and temporal locality. | Hugo Brunie, Costin Iancu, Khaled Z. Ibrahim, Philip Brisk, Brandon Cook |
| 2020 | VLSID | A Shared-Memory Parallel Implementation of the RePlAce Global Cell Placer. | Frdric Gessler, Philip Brisk, Mirjana Stojilovic |
| 2019 | CLOUD | Matrix Profile XIV: Scaling Time Series Motif Discovery with GPUs to Break a Quintillion Pairwise Comparisons a Day and Beyond. | Zachary Zimmerman, Kaveh Kamgar, Nader Shakibay Senobari, Brian Crites, Gareth J. Funning, Philip Brisk, Eamonn J. Keogh |
| 2019 | ICCAD | Specification, Integration, and Benchmarking of Continuous Flow Microfluidic Devices: Invited Paper. | Radhakrishna Sanka, Brian Crites, Jeffrey McDaniel, Philip Brisk, Douglas Densmore |
| 2019 | ICDM | Matrix Profile XVIII: Time Series Mining in the Face of Fast Moving Streams using a Learned Approximate Matrix Profile. | Zachary Zimmerman, Nader Shakibay Senobari, Gareth J. Funning, Evangelos E. Papalexakis, Samet Oymak, Philip Brisk, Eamonn J. Keogh |
| 2019 | NDSS | Oligo-Snoop: A Non-Invasive Side Channel Attack Against DNA Synthesis Machines. | Sina Faezi, Sujit Rokka Chhetri, Arnav Vaibhav Malawade, John Charles Chaput, William H. Grover, Philip Brisk, Mohammad Abdullah Al Faruque |
| 2018 | ASPDAC | Exploration of approximate multipliers design space using carry propagation free compressors. | Sina Boroumand, Hadi Parandeh-Afshar, Philip Brisk, Siamak Mohammadi |
| 2018 | CGO | A compiler for cyber-physical digital microfluidic biochips. | Christopher Curtis, Daniel T. Grissom, Philip Brisk |
| 2018 | DATE | Approximate quaternary addition with the fast carry chains of FPGAs. | Sina Boroumand, Hadi Parandeh-Afshar, Philip Brisk |
| 2018 | FPL | Deterministic Parallel Routing for FPGAs Based on Galois Parallel Execution Model. | Yehdhih Ould Mohammed Moctar, Mirjana Stojilovic, Philip Brisk |
| 2018 | ICCAD | HLSPredict: cross platform performance prediction for FPGA high-level synthesis. | Kenneth O'Neal, Mitch Liu, Hans Tang, Amin Kalantar, Kennen DeRenard, Philip Brisk |
| 2017 | ACSSC | From C to elastic circuits. | Lana Josipovic, Philip Brisk, Paolo Ienne |
| 2017 | DAC | Arbitrary Precision and Complexity Tradeoffs for Gate-Level Information Flow Tracking. | Andrew Becker, Wei Hu, Yu Tai, Philip Brisk, Ryan Kastner, Paolo Ienne |
| 2017 | DAC | HALWPE: Hardware-Assisted Light Weight Performance Estimation for GPUs. | Kenneth O'Neal, Philip Brisk, Emily Shriver, Michael Kishinevsky |
| 2017 | DATE | The case for semi-automated design of microfluidic very large scale integration (mVLSI) chips. | Jeffrey McDaniel, William H. Grover, Philip Brisk |
| 2017 | FCCM | An Out-of-Order Load-Store Queue for Spatial Computing. | Lana Josipovic, Philip Brisk, Paolo Ienne |
| 2016 | FPL | Preface. | Paolo Ienne, Walid A. Najjar, Jason Helge Anderson, Philip Brisk, Walter Stechele |
| 2016 | ICDM | Matrix Profile II: Exploiting a Novel Algorithm and GPUs to Break the One Hundred Million Barrier for Time Series Motifs and Joins. | Yan Zhu, Zachary Zimmerman, Nader Shakibay Senobari, Chin-Chia Michael Yeh, Gareth J. Funning, Abdullah Mueen, Philip Brisk, Eamonn J. Keogh |
| 2015 | VTS | Rapid online fault recovery for cyber-physical digital microfluidic biochips. | Christopher Jaress, Philip Brisk, Daniel T. Grissom |
| 2014 | ACSSC | Accelerating the dynamic time warping distance measure using logarithmetic arithmetic. | Joseph Tarango, Eamonn J. Keogh, Philip Brisk |
| 2014 | ASPDAC | Exploring speed and energy tradeoffs in droplet transport for digital microfluidic biochips. | Johnathan Fiske, Daniel T. Grissom, Philip Brisk |
| 2014 | DAC | Parallel FPGA Routing based on the Operator Formulation. | Yehdhih Ould Mohammed Moctar, Philip Brisk |
| 2013 | ASPDAC | Design and verification tools for continuous fluid flow-based microfluidic devices. | Jeffrey McDaniel, Auralila Baez, Brian Crites, Aditya Tammewar, Philip Brisk |
| 2013 | DAC | A field-programmable pin-constrained digital microfluidic biochip. | Daniel T. Grissom, Philip Brisk |
| 2013 | DATE | An EDA-friendly protection scheme against side-channel attacks. | Ali Galip Bayrak, Nikola Velickovic, Francesco Regazzoni, David Novo, Philip Brisk, Paolo Ienne |
| 2013 | FPL | Shared memory heterogeneous computation on PCIe-supported platforms. | Sambit Kumar Shukla, Yang Yang, Laxmi N. Bhuyan, Philip Brisk |
| 2013 | ICCAD | A just-in-time customizable processor. | Liang Chen, Joseph Tarango, Tulika Mitra, Philip Brisk |
| 2012 | DAC | Path scheduling on digital microfluidic biochips. | Daniel T. Grissom, Philip Brisk |
| 2012 | DATE | Selective flexibility: Breaking the rigidity of datapath merging. | Mirjana Stojilovic, David Novo, Lazar Saranovac, Philip Brisk, Paolo Ienne |
| 2012 | FPGA | Reducing the cost of floating-point mantissa alignment and normalization in FPGAs. | Yehdhih Ould Mohammed Moctar, Nithin George, Hadi Parandeh-Afshar, Paolo Ienne, Guy G. F. Lemieux, Philip Brisk |
| 2012 | FPL | Routing algorithms for FPGAS with sparse intra-cluster routing crossbars. | Yehdhih Ould Mohammed Moctar, Guy G. F. Lemieux, Philip Brisk |
| 2011 | CASES | Graph-coloring and treescan register allocation using repairing. | Quentin Colombet, Benoit Boissinot, Philip Brisk, Sebastian Hack, Fabrice Rastello |
| 2011 | DAC | A first step towards automatic application of power analysis countermeasures. | Ali Galip Bayrak, Francesco Regazzoni, Philip Brisk, Franois-Xavier Standaert, Paolo Ienne |
| 2011 | FPGA | Reducing the pressure on routing resources of FPGAs with generic logic chains. | Hadi Parandeh-Afshar, Grace Zgheib, Philip Brisk, Paolo Ienne |
| 2010 | ASPDAC | A high-level synthesis flow for custom instruction set extensions for application-specific processors. | Nagaraju Pothineni, Philip Brisk, Paolo Ienne, Anshul Kumar, Kolin Paul |
| 2010 | FPL | Synthesis of Floating-Point Addition Clusters on FPGAs Using Carry-Save Arithmetic. | Amit Verma, Ajay Kumar Verma, Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne |
| 2009 | ARITH | Challenges in Automatic Optimization of Arithmetic Circuits. | Ajay Kumar Verma, Philip Brisk, Paolo Ienne |
| 2009 | ASPDAC | Hybrid LZA: a near optimal implementation of the leading zero anticipator. | Amit Verma, Ajay Kumar Verma, Philip Brisk, Paolo Ienne |
| 2009 | CHES | A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions. | Francesco Regazzoni, Alessandro Cevrero, Franois-Xavier Standaert, Stphane Badel, Theo Kluter, Philip Brisk, Yusuf Leblebici, Paolo Ienne |
| 2009 | DAC | Thermal-aware data flow analysis. | Jos Luis Ayala, David Atienza, Philip Brisk |
| 2009 | DAC | Way Stealing: cache-assisted automatic instruction set extensions. | Theo Kluter, Philip Brisk, Paolo Ienne, Edoardo Charbon |
| 2009 | FCCM | FPGA Implementation of a Single-Precision Floating-Point Multiply-Accumulator with Single-Cycle Accumulation. | Arun Paidimarri, Alessandro Cevrero, Philip Brisk, Paolo Ienne |
| 2009 | FPGA | 3D configuration caching for 2D FPGAs. | Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Philip Brisk, Yusuf Leblebici, Paolo Ienne, Maurizio Skerlj |
| 2009 | FPL | Using 3D integration technology to realize multi-context FPGAs. | Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Maurizio Skerlj, Philip Brisk, Yusuf Leblebici, Paolo Ienne |
| 2009 | FPL | Exploiting fast carry-chains of FPGAs for designing compressor trees. | Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne |
| 2009 | ICCAD | Memory organization and data layout for instruction set extensions with architecturally visible storage. | Panagiotis Athanasopoulos, Philip Brisk, Yusuf Leblebici, Paolo Ienne |
| 2009 | ICCAD | Iterative layering: Optimizing arithmetic circuits by structuring the information flow. | Ajay Kumar Verma, Philip Brisk, Paolo Ienne |
| 2008 | ASPDAC | Efficient synthesis of compressor trees on FPGAs. | Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne |
| 2008 | ASPDAC | Fast, quasi-optimal, and pipelined instruction-set extensions. | Ajay Kumar Verma, Philip Brisk, Paolo Ienne |
| 2008 | CASES | Design space exploration for field programmable compressor trees. | Seyed-Hosein Attarzadeh-Niaki, Alessandro Cevrero, Philip Brisk, Chrysostomos Nicopoulos, Frank K. Grkaynak, Yusuf Leblebici, Paolo Ienne |
| 2008 | DATE | Improving Synthesis of Compressor Trees on FPGAs via Integer Linear Programming. | Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne |
| 2008 | DATE | Variable Latency Speculative Addition: A New Paradigm for Arithmetic Circuit Design. | Ajay Kumar Verma, Philip Brisk, Paolo Ienne |
| 2008 | FPGA | Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs. | Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay Kumar Verma, Philip Brisk, Frank K. Grkaynak, Yusuf Leblebici, Paolo Ienne |
| 2008 | FPGA | A novel FPGA logic block for improved arithmetic performance. | Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne |
| 2007 | CASES | An optimistic and conservative register assignment heuristic for chordal graphs. | Philip Brisk, Ajay Kumar Verma, Paolo Ienne |
| 2007 | CASES | Rethinking custom ISE identification: a new processor-agnostic method. | Ajay Kumar Verma, Philip Brisk, Paolo Ienne |
| 2007 | DAC | Enhancing FPGA Performance for Arithmetic Circuits. | Philip Brisk, Ajay Kumar Verma, Paolo Ienne, Hadi Parandeh-Afshar |
| 2007 | DAC | Progressive Decomposition: A Heuristic to Structure Arithmetic Circuits. | Ajay Kumar Verma, Philip Brisk, Paolo Ienne |
| 2007 | ICCAD | Optimal polynomial-time interprocedural register allocation for high-level synthesis and ASIP design. | Philip Brisk, Ajay Kumar Verma, Paolo Ienne |
| 2007 | SCOPES | Interference graphs for procedures in static single information form are interval graphs. | Philip Brisk, Majid Sarrafzadeh |
| 2006 | DATE | Layout driven data communication optimization for high level synthesis. | Ryan Kastner, Wenrui Gong, Xin Hao, Forrest Brewer, Adam Kaplan, Philip Brisk, Majid Sarrafzadeh |
| 2005 | SAC | Adaptive and fault tolerant medical vest for life-critical medical monitoring. | Roozbeh Jafari, Foad Dabiri, Philip Brisk, Majid Sarrafzadeh |
| 2004 | DAC | Area-efficient instruction set synthesis for reconfigurable system-on-chip designs. | Philip Brisk, Adam Kaplan, Majid Sarrafzadeh |
| 2004 | SCOPES | Instruction Selection for Compilers that Target Architectures with Echo Instructions. | Philip Brisk, Ani Nahapetian, Majid Sarrafzadeh |
| 2003 | DAC | Data communication estimation and reduction for reconfigurable systems. | Adam Kaplan, Philip Brisk, Ryan Kastner |
| 2002 | CASES | Instruction generation and regularity extraction for reconfigurable processors. | Philip Brisk, Adam Kaplan, Ryan Kastner, Majid Sarrafzadeh |