| 2026 | ISCAS | Fixed-Point Implementation Analysis of MLSE Receiver DSP for High-Speed Wireline Transceivers. | Dohyeon Kwon, Donggeon Kim, Yujin Choi, Yusuf Leblebici, Gain Kim |
| 2020 | ISCAS | A Low-Power 9-Bit 222 MS/s Asynchronous SAR ADC in 65 nm CMOS. | Ayca Akkaya, Firat Celik, Yusuf Leblebici |
| 2020 | ISCAS | Discrete Time Analysis of Phase Detector Linear Range Extension in Sub-Sampling PLL. | Duygu Kostak, Yusuf Leblebici |
| 2019 | DSD | Real-Time Textureless-Region Tolerant High-Resolution Depth Estimation System. | Bilal Demir, Jean-Philippe Thiran, Yusuf Leblebici |
| 2019 | ISCAS | Multi-ReRAM Synapses for Artificial Neural Network Training. | Irem Boybat, Cecilia Giovinazzo, Elmira Shahrabi, Igor Krawczuk, Iason Giannopoulos, Christophe Piveteau, Manuel Le Gallo, Carlo Ricciardi, Abu Sebastian, Evangelos Eleftheriou, Yusuf Leblebici |
| 2018 | IJCNN | Online Feature Learning from a non-i.i.d. Stream in a Neuromorphic System with Synaptic Competition. | Stanislaw Wozniak, Angeliki Pantazi, Yusuf Leblebici, Evangelos Eleftheriou |
| 2018 | ISCAS | Hardware Implementation of a Smart Camera with Keypoint Detection and Description. | Selman Ergnay, Yusuf Leblebici |
| 2018 | ISCAS | Parallel Implementation Technique of Digital Equalizer for Ultra-High-Speed Wireline Receiver. | Gain Kim, Lukas Kull, Danny Luu, Matthias Braendli, Christian Menolfi, Pier Andrea Francese, Cosimo Aprile, Thomas Morf, Marcel A. Kossel, Alessandro Cevrero, Ilter zkaya, Thomas Toifl, Yusuf Leblebici |
| 2017 | ICANN | Unsupervised Learning Using Phase-Change Synapses and Complementary Patterns. | Severin Sidler, Angeliki Pantazi, Stanislaw Wozniak, Yusuf Leblebici, Evangelos Eleftheriou |
| 2017 | IJCNN | Neuromorphic system with phase-change synapses for pattern learning and feature extraction. | Stanislaw Wozniak, Angeliki Pantazi, Yusuf Leblebici, Evangelos Eleftheriou |
| 2017 | ISCAS | Reducing circuit design complexity for neuromorphic machine learning systems based on Non-Volatile Memory arrays. | Pritish Narayanan, Lucas L. Sanches, Alessandro Fumarola, Robert M. Shelby, Stefano Ambrogio, Jun-Woo Jang, Hyunsang Hwang, Yusuf Leblebici, Geoffrey W. Burr |
| 2016 | ISCAS | A fully-digital spectrum shaping signaling for serial-data transceiver with crosstalk and ISI reduction property in multi-drop memory interfaces. | Kiarash Gharibdoust, Gain Kim, Armin Tajalli, Yusuf Leblebici |
| 2016 | ISCAS | Block matching based real-time optical flow hardware implementation. | Kerem Seyid, Andrea Richaud, Raffaele Capoccia, Yusuf Leblebici |
| 2015 | DATE | A ultra-low-power FPGA based on monolithically integrated RRAMs. | Pierre-Emmanuel Gaillardon, Xifan Tang, Jury Sandrini, Maxime Thammasack, Somayyeh Rahimian Omam, Davide Sacchetto, Yusuf Leblebici, Giovanni De Micheli |
| 2015 | ICIP | A low-power 490 mpixels/s hardware accelerator for pyramidal decomposition of images. | Vladan Popovic, Yusuf Leblebici |
| 2015 | ISCAS | Live demonstration: Real-time free viewpoint synthesis using three-camera disparity estimation hardware. | Abdulkadir Akin, Raffaele Capoccia, Jonathan Narinx, Jonathan Masur, Alexandre Schmid, Yusuf Leblebici |
| 2015 | ISCAS | Real-time free viewpoint synthesis using three-camera disparity estimation hardware. | Abdulkadir Akin, Raffaele Capoccia, Jonathan Narinx, Jonathan Masur, Alexandre Schmid, Yusuf Leblebici |
| 2015 | ISCAS | Design of high-temperature SRAM for reliable operation beyond 250°C. | Radisav Cojbasic, Yusuf Leblebici |
| 2015 | ISCAS | Low-voltage read/write circuit design for transistorless ReRAM crossbar arrays in 180nm CMOS technology. | Jury Sandrini, Tugba Demirci, Maxime Thammasack, Davide Sacchetto, Yusuf Leblebici |
| 2015 | ISCAS | Jitter analysis and measurement in subthreshold source-coupled differential ring oscillators. | Mahsa Shoaran, Armin Tajalli, Massimo Alioto, Yusuf Leblebici |
| 2014 | ISM | An Immersive Telepresence System Using a Real-Time Omnidirectional Camera and a Virtual Reality Head-Mounted Display. | Luis Manuel Gaemperle, Kerem Seyid, Vladan Popovic, Yusuf Leblebici |
| 2013 | DAC | Towards structured ASICs using polarity-tunable Si nanowire transistors. | Pierre-Emmanuel Gaillardon, Michele De Marchi, Luca Gaetano Amar, Shashikanth Bobba, Davide Sacchetto, Yusuf Leblebici, Giovanni De Micheli |
| 2013 | DATE | Fast and accurate BER estimation methodology for I/O links based on extreme value theory. | Alessandro Cevrero, Nestor E. Evmorfopoulos, Charalampos Antoniadis, Paolo Ienne, Yusuf Leblebici, Andreas Burg, Georgios I. Stamoulis |
| 2013 | DATE | Vertically-stacked double-gate nanowire FETs with controllable polarity: from devices to regular ASICs. | Pierre-Emmanuel Gaillardon, Luca Gaetano Amar, Shashikanth Bobba, Michele De Marchi, Davide Sacchetto, Yusuf Leblebici, Giovanni De Micheli |
| 2013 | DATE | 3D-MMC: a modular 3D multi-core architecture with efficient resource pooling. | Tiansheng Zhang, Alessandro Cevrero, Giulia Beanato, Panagiotis Athanasopoulos, Ayse K. Coskun, Yusuf Leblebici |
| 2013 | ICASSP | Compressive multichannel cortical signal recording. | Mahdad Hosseini Kamal, Mahsa Shoaran, Yusuf Leblebici, Alexandre Schmid, Pierre Vandergheynst |
| 2013 | ICASSP | Real-time hardware implementation of multi-resolution image blending. | Vladan Popovic, Kerem Seyid, Alexandre Schmid, Yusuf Leblebici |
| 2013 | ISCAS | Characterization of standard CMOS compatible photodiodes and pixels for Lab-on-Chip devices. | Gozen Koklu, Ralph Etienne-Cummings, Yusuf Leblebici, Giovanni De Micheli, Sandro Carrara |
| 2013 | ISCAS | A low-power area-efficient compressive sensing approach for multi-channel neural recording. | Mahsa Shoaran, Mariazel Maqueda Lopez, Vijaya Sankara Rao Pasupureddi, Yusuf Leblebici, Alexandre Schmid |
| 2013 | ISM | Spherical Panorama Construction Using Multi Sensor Registration Priors and Its Real-Time Hardware. | Omer Cogal, Vladan Popovic, Yusuf Leblebici |
| 2012 | DAC | Physical synthesis onto a Sea-of-Tiles with double-gate silicon nanowire transistors. | Shashikanth Bobba, Michele De Marchi, Yusuf Leblebici, Giovanni De Micheli |
| 2012 | DIAGRAMS | Design and Implementation of Multi-camera Systems Distributed over a Spherical Geometry. | Hossein Afshari, Kerem Seyid, Alexandre Schmid, Yusuf Leblebici |
| 2012 | DSD | Enhanced Omnidirectional Image Reconstruction Algorithm and Its Real-Time Hardware. | Abdulkadir Akin, Elif Erdede, Hossein Afshari, Alexandre Schmid, Yusuf Leblebici |
| 2012 | ISCAS | Quantitative comparison of commercial CCD and custom-designed CMOS camera for biological applications. | Gozen Koklu, Julien Ghaye, Rene Beuchat, Giovanni De Micheli, Yusuf Leblebici, Sandro Carrara |
| 2011 | DAC | Power-gated MOS current mode logic (PG-MCML): a power aware DPA-resistant standard cell library. | Alessandro Cevrero, Francesco Regazzoni, Micheal Schwander, Stphane Badel, Paolo Ienne, Yusuf Leblebici |
| 2011 | DATE | Towards thermally-aware design of 3D MPSoCs with inter-tier cooling. | Mohamed M. Sabry, Arvind Sridhar, David Atienza, Yuksel Temiz, Yusuf Leblebici, S. Szczukiewicz, Navid Borhani, John Richard Thome, Thomas Brunschwiler, Bruno Michel |
| 2011 | ICCAD | Alternative design methodologies for the next generation logic switch. | Davide Sacchetto, Michele De Marchi, Giovanni De Micheli, Yusuf Leblebici |
| 2011 | ISCAS | Area, throughput, and energy-efficiency trade-offs in the VLSI implementation of LDPC decoders. | Christoph Roth, Alessandro Cevrero, Christoph Studer, Yusuf Leblebici, Andreas Burg |
| 2010 | DATE | AVGS-Mux style: A novel technology and device independent technique for reducing power and compensating process variations in FPGA fabrics. | Bahman Kheradmand Boroujeni, Christian Piguet, Yusuf Leblebici |
| 2010 | DATE | Ultra-low power mixed-signal design platform using subthreshold source-coupled circuits. | Armin Tajalli, Yusuf Leblebici |
| 2010 | ISCAS | A (256256) pixel 76.7mW CMOS imager/ compressor based on real-time In-pixel compressive sensing. | Vahid Majidzadeh, Laurent Jacques, Alexandre Schmid, Pierre Vandergheynst, Yusuf Leblebici |
| 2010 | ISCAS | Memristive devices fabricated with silicon nanowire schottky barrier transistors. | Davide Sacchetto, M. Haykel Ben Jamaa, Sandro Carrara, Giovanni De Micheli, Yusuf Leblebici |
| 2010 | ISCAS | Design aspects of carry lookahead adders with vertically-stacked nanowire transistors. | Davide Sacchetto, M. Haykel Ben Jamaa, Giovanni De Micheli, Yusuf Leblebici |
| 2010 | ISCAS | Selective redundancy-based design techniques for the minimization of local delay variations. | Milos Stanisavljevic, Alexandre Schmid, Yusuf Leblebici |
| 2009 | ASPDAC | A stochastic perturbative approach to design a defect-aware thresholder in the sense amplifier of crossbar memories. | M. Haykel Ben Jamaa, David Atienza, Yusuf Leblebici, Giovanni De Micheli |
| 2009 | CASES | Complete nanowire crossbar framework optimized for the multi-spacer patterning technique. | M. Haykel Ben Jamaa, Gianfranco Cerofolini, Yusuf Leblebici, Giovanni De Micheli |
| 2009 | CHES | A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions. | Francesco Regazzoni, Alessandro Cevrero, Franois-Xavier Standaert, Stphane Badel, Theo Kluter, Philip Brisk, Yusuf Leblebici, Paolo Ienne |
| 2009 | DAC | Decoding nanowire arrays fabricated with the multi-spacer patterning technique. | M. Haykel Ben Jamaa, Yusuf Leblebici, Giovanni De Micheli |
| 2009 | DATE | Dynamic thermal management in 3D multicore architectures. | Ayse K. Coskun, Jos L. Ayala, David Atienza, Tajana Simunic Rosing, Yusuf Leblebici |
| 2009 | FPGA | 3D configuration caching for 2D FPGAs. | Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Philip Brisk, Yusuf Leblebici, Paolo Ienne, Maurizio Skerlj |
| 2009 | FPL | Using 3D integration technology to realize multi-context FPGAs. | Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Maurizio Skerlj, Philip Brisk, Yusuf Leblebici, Paolo Ienne |
| 2009 | ICASSP | CMOS compressed imaging by Random Convolution. | Laurent Jacques, Pierre Vandergheynst, Alexandre Bibet, Vahid Majidzadeh, Alexandre Schmid, Yusuf Leblebici |
| 2009 | ICCAD | Memory organization and data layout for instruction set extensions with architecturally visible storage. | Panagiotis Athanasopoulos, Philip Brisk, Yusuf Leblebici, Paolo Ienne |
| 2009 | IJCNN | A pulse-density modulation circuit exhibiting noise shaping with single-electron neurons. | Andrew Kilinga Kikombo, Tetsuya Asai, Takahide Oya, Alexandre Schmid, Yusuf Leblebici, Yoshihito Amemiya |
| 2009 | ISCAS | Optimization of Wire Grid Size for Differential Routing and Impact on the Power-delay-area Tradeoff. | Massimo Alioto, Stphane Badel, Yusuf Leblebici |
| 2009 | ISCAS | Analysis and Design of Ultra-low Power Subthreshold MCML Gates. | Massimo Alioto, Yusuf Leblebici |
| 2009 | ISCAS | Load Optimization of an Inductive Power Link for Remote Powering of Biomedical Implants. | Kanber Mithat Silay, Denis Dondi, Luca Larcher, Michel J. Declercq, Luca Benini, Yusuf Leblebici, Catherine Dehollain |
| 2009 | ISCAS | Subthreshold Leakage Reduction: A Comparative Study of SCL and CMOS Design. | Armin Tajalli, Yusuf Leblebici |
| 2008 | CASES | Design space exploration for field programmable compressor trees. | Seyed-Hosein Attarzadeh-Niaki, Alessandro Cevrero, Philip Brisk, Chrysostomos Nicopoulos, Frank K. Grkaynak, Yusuf Leblebici, Paolo Ienne |
| 2008 | DAC | Programmable logic circuits based on ambipolar CNFET. | M. Haykel Ben Jamaa, David Atienza, Yusuf Leblebici, Giovanni De Micheli |
| 2008 | DATE | A Generic Standard Cell Design Methodology for Differential Circuit Styles. | Stphane Badel, Erdem Guleyupoglu, Ozgur Inac, Anna Pena Martinez, Paolo Vietti, Frank K. Grkaynak, Yusuf Leblebici |
| 2008 | DATE | Novel Front-End Circuit Architectures for Integrated Bio-Electronic Interfaces. | Carlotta Guiducci, Alexandre Schmid, Frank K. Grkaynak, Yusuf Leblebici |
| 2008 | FPGA | Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs. | Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay Kumar Verma, Philip Brisk, Frank K. Grkaynak, Yusuf Leblebici, Paolo Ienne |
| 2008 | ISCAS | Improving the power-delay product in SCL circuits using source follower output stage. | Armin Tajalli, Frank K. Grkaynak, Yusuf Leblebici, Massimo Alioto, Elizabeth J. Brauer |
| 2007 | ICCAD | Fault-tolerant multi-level logic decoder for nanoscale crossbar memory arrays. | M. Haykel Ben Jamaa, Kirsten E. Moselund, David Atienza, Didier Bouvet, Adrian M. Ionescu, Yusuf Leblebici, Giovanni De Micheli |
| 2007 | ISCAS | Breaking the Power-Delay Tradeoff: Design of Low-Power High-Speed MOS Current-Mode Logic Circuits Operating with Reduced Supply Voltage. | Stphane Badel, Yusuf Leblebici |
| 2006 | IJCNN | Fault-Tolerance of Robust Feed-Forward Architecture Using Single-Ended and Differential Deep-Submicron Circuits Under Massive Defect Density. | Milos Stanisavljevic, Alexandre Schmid, Yusuf Leblebici |
| 2006 | ISCAS | Weak inversion performance of CMOS and DCVSPG logic families in sub-300 mV range. | Omer Can Akgun, Yusuf Leblebici |
| 2006 | ISCAS | Via-programmable expanded universal logic gate in MCML for structured ASIC applications: circuit design. | Elizabeth J. Brauer, Ilhan Hatirnaz, Stphane Badel, Yusuf Leblebici |
| 2006 | ISCAS | Analysis and modeling of jitter and frequency tolerance in gated oscillator based CDRs. | Armin Tajalli, Paul Muller, Seyed Mojtaba Atarodi, Yusuf Leblebici |
| 2005 | DATE | Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit. | Paul Muller, Armin Tajalli, Seyed Mojtaba Atarodi, Yusuf Leblebici |
| 2005 | FDL | Jitter Tolerance Analysis of Clock and Data Recovery Circuits. | Paul Muller, Yusuf Leblebici |
| 2005 | ISCAS | Quantitative modelling and comparison of communication schemes to guarantee quality-of-service in networks-on-chip. | Mehmet Derin Harmanci, Nuria Pazos Escudero, Yusuf Leblebici, Paolo Ienne |
| 2005 | ISCAS | Single-electron circuit for inhibitory spiking neural network with fault-tolerant architecture. | Takahide Oya, Tetsuya Asai, Yoshihito Amemiya, Alexandre Schmid, Yusuf Leblebici |
| 2005 | ISCAS | Low-power current mode logic for improved DPA-resistance in embedded systems. | Zeynep Toprak Deniz, Yusuf Leblebici |
| 2005 | ISLPED | A low-power, multichannel gated oscillator-based CDR for short-haul applications. | Armin Tajalli, Paul Muller, Seyed Mojtaba Atarodi, Yusuf Leblebici |
| 2004 | IJCNN | Fault-tolerant PLA-style circuit design for failure-prone nanometer CMOS and quantum device technologies. | Alexandre Schmid, Yusuf Leblebici |
| 2004 | ISCAS | Mixed analog-digital image processing circuit based on Hamming artificial neural network architecture. | Stphane Badel, Alexandre Schmid, Yusuf Leblebici |
| 2004 | ISCAS | Modelling and implementation of twisted differential on-chip interconnects for crosstalk noise reduction. | Ilhan Hatirnaz, Yusuf Leblebici |
| 2004 | ISCAS | Robust and fault-tolerant circuit design for nanometer-scale devices and single-electron transistors. | Alexandre Schmid, Yusuf Leblebici |
| 2003 | ESANN | VLSI Realization of a Two-Dimensional Hamming Distance Comparator ANN for Image Processing Applications. | Stphane Badel, Alexandre Schmid, Yusuf Leblebici |
| 2003 | IJCNN | A VLSI Hamming artificial neural network with k-winner-take-all and k-loser-take-all capability. | Stphane Badel, Alexandre Schmid, Yusuf Leblebici |
| 2003 | ISCAS | Full-custom CMOS realization of a high-performance binary sorting engine with linear area-time complexity. | Turan Demirci, Ilhan Hatirnaz, Yusuf Leblebici |
| 2003 | ISCAS | Design and realization of a modular 200 MSample/s 12-bit pipelined A/D converter block using deep-submicron digital CMOS technology. | Zeynep Toprak Deniz, Yusuf Leblebici |
| 2000 | ICASSP | A compact modular architecture for high-speed binary sorting. | Ilhan Hatirnaz, Frank K. Grkaynak, Yusuf Leblebici |
| 2000 | ISCAS | Higher radix Kogge-Stone parallel prefix adder architectures. | Frank K. Grkaynak, Yusuf Leblebici, Laurent Chaouat, Patrik J. McGuinness |
| 2000 | ISCAS | A compact modular architecture for the realization of high-speed binary sorting engines based on rank ordering. | Ilhan Hatirnaz, Frank K. Grkaynak, Yusuf Leblebici |
| 1999 | IJCNN | A two-stage charge-based analog/digital neuron circuit with adjustable weights. | Alexandre Schmid, Yusuf Leblebici, Daniel Mlynek |
| 1999 | ISCAS | Realization of a programmable rank-order filter architecture using capacitive threshold logic gates. | Ilhan Hatirnaz, Frank K. Grkaynak, Yusuf Leblebici |
| 1999 | ISCAS | A novel analog-digital flash converter architecture based on capacitive threshold gates. | Alexandre Schmid, D. Bowler, R. Baumgartner, Yusuf Leblebici |
| 1991 | ICCAD | New Simulation Methods for MOS VLSI Timing and Reliability. | Yung-Ho Shih, Yusuf Leblebici, Sung-Mo Kang |
| 1990 | ICCAD | An Integrated Hot-Carrier Degradation Simulator for VLSI Reliability Analysis. | Yusuf Leblebici, Sung-Mo Kang |
| 1989 | ICCD | Simulation of MOS circuit performance degradation with emphasis on VLSI design-for-reliability. | Yusuf Leblebici, Sung-Mo Kang |
| 1988 | ICCAD | An efficient method for circuit sensitivity calculation using piecewise linear waveform models. | Sung-Mo Kang, Yusuf Leblebici |