Alessandro Cevrero
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
11
Venues
8
Active years
2008–2018
Best venue rank
A*
Where they publish
Papers
11 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2018 | ISCAS | Parallel Implementation Technique of Digital Equalizer for Ultra-High-Speed Wireline Receiver. | Gain Kim, Lukas Kull, Danny Luu, Matthias Braendli, Christian Menolfi, Pier Andrea Francese, Cosimo Aprile, Thomas Morf, Marcel A. Kossel, Alessandro Cevrero, Ilter zkaya, Thomas Toifl, Yusuf Leblebici |
| 2013 | DATE | Fast and accurate BER estimation methodology for I/O links based on extreme value theory. | Alessandro Cevrero, Nestor E. Evmorfopoulos, Charalampos Antoniadis, Paolo Ienne, Yusuf Leblebici, Andreas Burg, Georgios I. Stamoulis |
| 2013 | DATE | 3D-MMC: a modular 3D multi-core architecture with efficient resource pooling. | Tiansheng Zhang, Alessandro Cevrero, Giulia Beanato, Panagiotis Athanasopoulos, Ayse K. Coskun, Yusuf Leblebici |
| 2011 | DAC | Power-gated MOS current mode logic (PG-MCML): a power aware DPA-resistant standard cell library. | Alessandro Cevrero, Francesco Regazzoni, Micheal Schwander, Stphane Badel, Paolo Ienne, Yusuf Leblebici |
| 2011 | ISCAS | Area, throughput, and energy-efficiency trade-offs in the VLSI implementation of LDPC decoders. | Christoph Roth, Alessandro Cevrero, Christoph Studer, Yusuf Leblebici, Andreas Burg |
| 2009 | CHES | A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions. | Francesco Regazzoni, Alessandro Cevrero, Franois-Xavier Standaert, Stphane Badel, Theo Kluter, Philip Brisk, Yusuf Leblebici, Paolo Ienne |
| 2009 | FCCM | FPGA Implementation of a Single-Precision Floating-Point Multiply-Accumulator with Single-Cycle Accumulation. | Arun Paidimarri, Alessandro Cevrero, Philip Brisk, Paolo Ienne |
| 2009 | FPGA | 3D configuration caching for 2D FPGAs. | Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Philip Brisk, Yusuf Leblebici, Paolo Ienne, Maurizio Skerlj |
| 2009 | FPL | Using 3D integration technology to realize multi-context FPGAs. | Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Maurizio Skerlj, Philip Brisk, Yusuf Leblebici, Paolo Ienne |
| 2008 | CASES | Design space exploration for field programmable compressor trees. | Seyed-Hosein Attarzadeh-Niaki, Alessandro Cevrero, Philip Brisk, Chrysostomos Nicopoulos, Frank K. Grkaynak, Yusuf Leblebici, Paolo Ienne |
| 2008 | FPGA | Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs. | Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay Kumar Verma, Philip Brisk, Frank K. Grkaynak, Yusuf Leblebici, Paolo Ienne |