| 2026 | Out with LSQs: Custom Circuits for Memory Access Reordering in Dynamic HLS. | Rouzbeh Pirayadi, Ayatallah Elakhras, Mirjana Stojilovic, Paolo Ienne |
| 2026 | Untitled record | Dave Ojika, Projjal Gupta, Preethi Budi, Herman Lam, Shreya Mehrotra |
| 2026 | Analysis and Optimization of Input-Dependent Stream Processing Pipelines on FPGAs. | Shashank Obla, Bin Li, James C. Hoe |
| 2026 | AI-Assisted Copilot Automation for Reliable FPGA Verification at Hyperscale. | Linh Nguyen, Nguyen Le, Tony-Dat Tran, Jagannath Panduranga Rao, Andrew Putnam |
| 2026 | HiLFS: FPGA-Orchestrated File System for High-Level Synthesis. | YoungSeok Na, Linus Y. Wong, Andr DeHon, Jing Jane Li |
| 2026 | ViM-Q: Energy Efficient Algorithm-Hardware Co-Design for Dynamically Quantized Vision Mamba Models. | Shengzhe Lyu, Yuhan She, Patrick S. Y. Hung, Ray C. C. Cheung, Weitao Xu |
| 2026 | HFRWKV: A High-Performance Fully On-Chip Hardware Accelerator for RWKV. | Shijie Liu, Zhenghao Zeng, Han Jiao, Yihua Huang |
| 2026 | CXL-SpecKV: A Disaggregated FPGA Speculative KV-Cache for Datacenter LLM Serving. | Dong Liu, Yanxuan Yu |
| 2026 | CODESCA: Co-Design for Spectral Clustering Acceleration. | Zhengyan Liu, Ce Guo, Zehuan Zhang, Qiang Liu, Wayne Luk |
| 2026 | RND: A Mixed-Grained Parallel Routing Framework with Region-based Net Decomposition for UltraScale FPGAs. | Wenhao Lin, Zewen Li, Xinshi Zang, Evangeline F. Y. Young |
| 2026 | MegaTurbo: A Scalable FPGA-based Engine for MegaFlow Classifier in Open vSwitch. | Sheng Lan, Ying Li, Zhongxian Liang, Wenjun Li, Yao Xin, Ying Wan, Hui Li, Weizhe Zhang |
| 2026 | MARU: An ML-Based Framework for Area Estimation from FPGA Resource Usage. | Tarun Kholay, Anup Ashok Kedilaya, Aman Arora, Jaydeep P. Kulkarni, Lizy K. John |
| 2026 | EagerlyElastic: Correct-by-Construction Eager Execution in Dynamically-Scheduled HLS. | Shun Katsumi, Emmet Murphy, Lana Josipovic |
| 2026 | Enabling Efficient SpMM for Sparse Attention on GEMM-Optimized Hardware with Block Aggregation. | Tianchu Ji, Niranjan Balasubramanian, Michael Ferdman, Peter A. Milder |
| 2026 | Improving Area Efficiency in Synthesizable eFPGA with Multi-output Logic Cell and Domain-Specific Routing Architecture. | Ryo Iwasaki, Tatsuya Sasaki, Yumi Iseki, Sota Kohata, Miyu Yoshida, Kenshu Seto, Masahiro Iida |
| 2026 | KANEL: Kolmogorov-Arnold Networks for Efficient LUT-based Evaluation. | Duc Hoang, Aarush Gupta, Philip C. Harris |
| 2026 | PROM: Protection against Reverse Engineering Attacks through Programmable Logic Macros. | Pravin Gaikwad, Aritra Dasgupta, Sudipta Paria, Peyman Dehghanzadeh, Jonathan Cruz, Swarup Bhunia |
| 2026 | Bridging the Gap: A Module-Context Modeling Methodology for Hyperscale FPGA Applications. | Madison N. Emas, Austin Baylis, Greg Stitt |
| 2026 | Exploring Real-Time Power Electronics Simulation on AMD AIEs. | Shouyu Du, Zhenyu Xu, Miaoxiang Yu, Jillian Cai, Yeonho Jeong, Tao Wei |
| 2026 | Synchronized CPU-FPGA Tracing for Heterogeneous Platforms. | Nicolas Deloumeau, Tarek Ould-Bachir, David Evans, Andrew Handke, Jamie Sanderson, Franois Tetreault |
| 2026 | Finding and Understanding Bugs in FPGA Place-and-Route Engines. | Ollie Cosgrove, Alastair F. Donaldson, John Wickerson |
| 2026 | vFPGA: Towards Sub-s Reconfiguration via 3D FPGA and Packaging Co-Design. | Nikhil K. Cherukuri, Sharad Nag, Pragnya Sudershan Nalla, Ashish K. Kola, Chetan S. Gadireddi, Kevin Dai, Jae-sun Seo, Zhenman Fang, Jeff Zhang, Yu Cao |
| 2026 | Gatling-V: An FPGA-based RISC-V Vector Core with Single-Issue, Multiple In-Flight Instruction Execution. | Farid Chalabi, Guy Lemieux |
| 2026 | NysX: An Accurate and Energy-Efficient FPGA Accelerator for Hyperdimensional Graph Classification at the Edge. | Jebacyril Arockiaraj, Dhruv Parikh, Viktor K. Prasanna |
| 2026 | Attest Like Software: Formally-Verified Software-Programmable Proof of Execution Architecture Using SoC FPGAs. | Fatemeh Arkannezhad, Nader Sehatbakhsh |