| 2026 | FlexMSM: A Flexible FPGA-Based Accelerator for Multi-Scalar Multiplication with Reconfigurable Modular Arithmetic and Optimized Pippenger Scheduling. | Cheng Chen, Gangqiang Yang, Hongchao Zhou, Hailiang Xiong, Zhiguo Wan |
| 2026 | Hummingbird+: Advancing FPGA-based LLM Deployment from Research Prototype to Edge Product. | Jindong Li, Tenglong Li, Guobin Shen, Dongcheng Zhao, Qian Zhang, Yi Zeng |
| 2026 | A2H-MAS: An Algorithm-to-HLS Multi-Agent System for Automated and Reliable FPGA Implementation. | Jie Lei, Ruofan Jia, J. Andrew Zhang, Hao Zhang |
| 2026 | AgRefactor: Refactoring for HLS Compatibility with a Self-Evolving Agentic Workflow. | Yang Zou, Zijian Ding, Chi Wang, Yizhou Sun, Jason Cong |
| 2025 | ARIES: An Agile MLIR-Based Compilation Flow for Reconfigurable Devices with AI Engines. | Jinming Zhuang, Shaojie Xiang, Hongzheng Chen, Niansong Zhang, Zhuoping Yang, Tony Mao, Zhiru Zhang, Peipei Zhou |
| 2025 | Measuring the Minimum Power Requirement of FPGA Architectural Specifications. | Andy Gean Ye, Anas Razzaq |
| 2025 | HiGTR: High-Performance FPGA Implementation of Complete GNN-based Trajectory Reconstruction for HEP. | Yun-Chen Yang, Hsuan-Wei Yu, Bo-Cheng Lai, Shih-Chieh Hsu, Mark S. Neubauer, Santosh Parajuli |
| 2025 | BAQET: BRAM-aware Quantization for Efficient Transformer Inference via Stream-based Architecture on an FPGA. | LingChi Yang, Chi-Jui Chen, Trung Le, Bo-Cheng Lai, Scott Hauck, Shih-Chieh Hsu |
| 2025 | Tile-Level Pipeline for Linear Scalable Stencil Computation on AMD AI Engines. | Zhenyu Xu, Miaoxiang Yu, Yazhe Zhang, Jillian Cai, Qing Yang, Tao Wei |
| 2025 | Hercules: Efficient Verification of High-Level Synthesis Designs with FPGA Acceleration. | Shuoxiang Xu, Zijian Jiang, Yuxin Zhang, David Boland, Yungang Bao, Kan Shi |
| 2025 | FAST: FPGA Acceleration of Fully Homomorphic Encryption with Efficient Bootstrapping. | Zhihan Xu, Tian Ye, Rajgopal Kannan, Viktor K. Prasanna |
| 2025 | FPGA-Only Implementation of MIPI C-PHY Receiver Using Blind Oversampling CDR for CMOS Image Sensors. | Jun Yeon Won, Shinki Jeong, Seongkwan Lee, Minho Kang, Insu Yang, Jaemoo Choi |
| 2025 | Greater than the Sum of its LUTs: Scaling Up LUT-based Neural Networks with AmigoLUT. | Olivia Weng, Marta Andronic, Danial Zuberi, Jiaqing Chen, Caleb Geniesse, George A. Constantinides, Nhan Tran, Nicholas J. Fraser, Javier Mauricio Duarte, Ryan Kastner |
| 2025 | Lessons from 40 Years of Reconfigurable Computing. | John Wawrzynek |
| 2025 | HEDWIG: Homomorphic Encryption Accelerator Design Using BFV-HPS With HiGh-Speed Fixed-Point Approximation. | Antian Wang, Weihang Tan, Zhenyu Xu, Tao Wei, Caiwen Ding, Keshab K. Parhi, Yingjie Lao |
| 2025 | Systolic Sparse Tensor Slices: FPGA Building Blocks for Sparse and Dense AI Acceleration. | Endri Taka, Ning-Chi Huang, Chi-Chih Chang, Kai-Chiang Wu, Aman Arora, Diana Marculescu |
| 2025 | Dynamic Loop Fusion in High-Level Synthesis. | Robert Szafarczyk, Syed Waqar Nabi, Wim Vanderbauwhede |
| 2025 | Resource Scheduling for Real-Time Machine Learning. | Suyash Vardhan Singh, Iftakhar Ahmad, David Andrews, Miaoqing Huang, Austin R. J. Downey, Jason D. Bakos |
| 2025 | Architectures for AI. | Steven K. Reinhardt |
| 2025 | A Unified Framework for Automated Code Transformation and Pragma Insertion. | Stphane Pouget, Louis-Nol Pouchet, Jason Cong |
| 2025 | RRNS Arith Lib - An Open-Source Redundant Residue Number System Arithmetic VHDL Library. | Tim Oberschulte, Enno Sievers, Holger Blume |
| 2025 | HUMA: Heterogeneous, Ultra Low-Latency Model Accelerator for The Virtual Brain on a Versal Adaptive SoC. | Amirreza Movahedin, Lennart P. L. Landsmeer, Christos Strydis |
| 2025 | Performance Analysis of GEMM Workloads on the AMD Versal Platform. | Kaustubh Manohar Mhatre, Venkata Guru Prasanth Mulleti, Curt John Bansil, Endri Taka, Aman Arora |
| 2025 | FMC-LLM: Enabling FPGAs for Efficient Batched Decoding of 70B+ LLMs with a Memory-Centric Streaming Architecture. | Wenheng Ma, Xinhao Yang, Shulin Zeng, Tengxuan Liu, Libo Shen, Hongyi Wang, Shiyao Li, Jiewen Wang, Yuhan Zhang, Hao Guo, Jintao Li, Ziming Zhang, Zhenhua Zhu, Xuefei Ning, Tsung-Yi Ho, Guohao Dai, Yu Wang |
| 2025 | SAT-Accel: A Modern SAT Solver on a FPGA. | Michael Lo, Mau-Chung Frank Chang, Jason Cong |