| 2025 | DPUV4E: High-Throughput DPU Architecture Design for CNN on Versal ACAP. | Guoyu Li, Pengbo Zheng, Jian Weng, Enshan Yang |
| 2025 | FlightVGM: Efficient Video Generation Model Inference with Online Sparsification and Hybrid Precision on FPGAs. | Jun Liu, Shulin Zeng, Li Ding, Widyadewi Soedarmadji, Hao Zhou, Zehao Wang, Jinhao Li, Jintao Li, Yadong Dai, Kairui Wen, Shan He, Yaqi Sun, Yu Wang, Guohao Dai |
| 2025 | PipeLink: A Pipelined Resource Sharing System for Dataflow High-Level Synthesis. | Rui Li, Rajit Manohar |
| 2025 | TAPCA: An Interface-Aware Cache Management Framework for Task Partitioning on CPU-FPGA SoC Platforms. | Enlai Li, Zhe Lin, Sharad Sinha, Wei Zhang |
| 2025 | TreeLUT: An Efficient Alternative to Deep Neural Networks for Inference Acceleration Using Gradient Boosted Decision Trees. | Alireza Khataei, Kia Bazargan |
| 2025 | Neural Network Inference in High-Performance Computing: Closing the Gap for FINN based Reconfigurable Accelerators. | Linus Jungemann, Bjarne Wintermann, Heinrich Riebler, Christian Plessl |
| 2025 | Towards Accelerator Customization in Real-time Safety-critical Systems. | Shixin Ji, Xingzhen Chen, Wei Zhang, Zhuoping Yang, Jinming Zhuang, Sarah Schultz, Yukai Song, Jingtong Hu, Alex K. Jones, Zheng Dong, Peipei Zhou |
| 2025 | InTRRA: Inter-Task Resource-Repurposing Accelerator for Efficient Transformer Inference on FPGAs. | Zifan He, Hersh Gupta, Huifeng Ke, Jason Cong |
| 2025 | wa-hls4ml and lui-gnn: A Benchmark and GNN based Surrogate Model for hls4ml Resource and Latency Estimation. | Benjamin Hawks, Dennis Plotnikov, Nhan Tran, Karla Tame-Narvaez, Mohammad Mehdi Rahimifar, Hamza Ezzaoui Rahali, Audrey C. Therrien, Giuseppe Di Guglielmo, Javier Duarte, Vladimir Loncar |
| 2025 | Enhancing FPGAs with Analog In-Memory Computing Macros. | Archit Gajjar, Lei Zhao, Omar Eldash, Aishwarya Natarajan, Rand Jean, Xia Sheng, Giacomo Pedretti, Paolo Faraboschi, Jim Ignowski, Luca Buonanno |
| 2025 | CIVIC-FPGA: A Trusted FPGA Design Validation by Multi-Tenant Cloud Providers. | Yu Feng, Zhaoqi Wang, Christophe Bobda |
| 2025 | High Throughput Low Latency Network Intrusion Detection on FPGAs: A Raw Packet Approach. | Muhammad Ali Farooq, Abid Rafique, Suhaib A. Fahmy, Aman Arora |
| 2025 | No Time to Lose: Enabling Real-Time Fluorescence Lifetime Imaging on Resource-constrained FPGAs Through Efficient Scheduling. | Ismail Erbas, Aporva Amarnath, Vikas Pandey, Karthik Swaminathan, Naigang Wang, Xavier Intes |
| 2025 | An Empirical Comparision of LLM-based Hardware Design and High-level Synthesis. | Fan Cui, Youwei Xiao, Kexing Zhou, Yun Liang |
| 2025 | FRIDA: Reconfigurable Arrays for Dynamically Scheduled High-Level Synthesis. | Louis Coulon, Lucas Ramirez, Jason Helge Anderson, Mirjana Stojilovic, Paolo Ienne |
| 2025 | An Efficient Traversal Method for FPGA Interconnect Testing Based on Regular Routing. | Wenwei Chen, Lin Ye, XiaoTong Zhao, Tongshu Ding, Jian Wang, Jinmei Lai |
| 2025 | Latency Insensitivity Testing for Dataflow HLS Designs. | Jianyi Cheng, Lianghui Wang, Zijian Jiang, Yungang Bao, Kan Shi |
| 2025 | ReducedLUT: Table Decomposition with "Don't Care" Conditions. | Oliver Cassidy, Marta Andronic, Samuel Coward, George A. Constantinides |
| 2025 | Two-Phase Transistor Sizing for FPGAs via Bayesian Optimization. | Xianfeng Cao, Huizhen Kuang, Yuanqi Wang, Lingli Wang |
| 2025 | FPGA Implementation of a 1D-CNN Modulation Classifier for Radar Signals. | Edgard Cansio |
| 2025 | FPGA-Oriented Design Space Exploration of a Real-Time Road Scene Semantic Segmentation Deep Neural Network. | Hugo Le Blevec, Mathieu Lonardon, Stefan Weithoffer, Matthieu Arzel |
| 2025 | Stream-HLS: Towards Automatic Dataflow Acceleration. | Suhail Basalama, Jason Cong |
| 2025 | OLA: An FPGA-based Overlay Accelerator for Privacy Preserving Machine Learning with Homomorphic Encryption. | Yang Yang, Rajgopal Kannan, Viktor K. Prasanna |
| 2025 | Seamless Acceleration of Fortran Intrinsics via AMD AI Engines. | Nick Brown, Gabriel Rodriguez-Canal |
| 2024 | SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration. | Jinming Zhuang, Zhuoping Yang, Shixin Ji, Heng Huang, Alex K. Jones, Jingtong Hu, Yiyu Shi, Peipei Zhou |