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Paper
Two-Phase Transistor Sizing for FPGAs via Bayesian Optimization.
Xianfeng Cao
,
Huizhen Kuang
,
Yuanqi Wang
,
Lingli Wang
Venue
A
FPGA
Year
2025
Proceedings
FPGA
DBLP record
conf/fpga/CaoKWW25 ↗
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