Xianfeng Cao
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
4
Venues
4
Active years
2025–2026
Best venue rank
C
Where they publish
Papers
4 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2026 | ISCAS | RL-FRA: Exploration and Optimization of FPGA Routing Architectures via Model-Based Reinforcement Learning. | Yuanqi Wang, Xianfeng Cao, Lingli Wang |
| 2025 | FPGA | Two-Phase Transistor Sizing for FPGAs via Bayesian Optimization. | Xianfeng Cao, Huizhen Kuang, Yuanqi Wang, Lingli Wang |
| 2025 | FPL | FLAIC: A Novel FPGA Logic Architecture via Fine-Grained Cut Topology Analysis. | Xianfeng Cao, Huizhen Kuang, Yuanqi Wang, Lingli Wang |
| 2025 | ICCAD | DynVec: An End-to-End Framework for Efficient Vector-Dataflow Execution. | Jiangnan Li, Xianfeng Cao, Kaixiang Zhu, Wenbo Yin, Lingli Wang |