Tile-Level Pipeline for Linear Scalable Stencil Computation on AMD AI Engines.
Zhenyu Xu, Miaoxiang Yu, Yazhe Zhang, Jillian Cai, Qing Yang, Tao Wei
Browse the full FPGA paper archive.
Zhenyu Xu, Miaoxiang Yu, Yazhe Zhang, Jillian Cai, Qing Yang, Tao Wei
Browse the full FPGA paper archive.