Hideharu Amano
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
148
Venues
33
Active years
1983–2026
Best venue rank
A*
Where they publish
- BFPL53 papers
- BASPDAC17 papers
- BICPP13 papers
- NationalPDPTA10 papers
- CPDP6 papers
- NationalFCCM5 papers
- A*ISCA4 papers
- CCLUSTER3 papers
- ADATE3 papers
- BAINA3 papers
- CISCAS2 papers
- CPDCAT2 papers
- CSNPD2 papers
- A*DAC2 papers
- A*HPCA2 papers
- AISLPED2 papers
- BRTCSA2 papers
- CISPA2 papers
- CDDECS1 paper
- BICPADS1 paper
- BNSS1 paper
- CICA3PP1 paper
- A*MICRO1 paper
- NationalVLSID1 paper
- CICCD1 paper
- AFPGA1 paper
- AIROS1 paper
- CEUC1 paper
- BCCGRID1 paper
- NationalCATA1 paper
- NationalHOTI1 paper
- AHPDC1 paper
- BEuroPar1 paper
Papers
148 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2026 | ISCAS | A 3-day ASIC Design Hands-on with the Minimal Fab. | Hideharu Amano, Atsutake Kosuge, Hirofumi Sumi, Naonobu Shimamoto, Yukinori Ochiai, Yurie Inoue, Tohru Mogami, Yoshio Mita, Makoto Ikeda |
| 2025 | ISCAS | An SoC Design and Fabrication Hands-On Educational Course within One Week Using Structured ASIC. | Hideharu Amano, Atsutake Kosuge, Hirofumi Sumi, Naonobu Shimamoto, Yukinori Ochiai, Yurie Inoue, Tohru Mogami, Yoshio Mita, Makoto Ikeda |
| 2022 | FPL | Optimizing Application Mapping for Multi-FPGA Systems with Multi-ejection STDM Switches. | Kohei Ito, Ryota Yasudo, Hideharu Amano |
| 2022 | FPL | FPL Demo: An FPGA-IP Prototype Chip for MEC devices. | Morihiro Kuga, Masahiro Iida, Hideharu Amano |
| 2022 | PDCAT | A Hardware Trojan Exploiting Coherence Protocol on NoCs. | Yoshiya Shikama, Michihiro Koibuchi, Hideharu Amano |
| 2022 | PDP | An efficient compilation of coarse-grained reconfigurable architectures utilizing pre-optimized sub-graph mappings. | Ayaka Ohwada, Takuya Kojima, Hideharu Amano |
| 2022 | SNPD | Reconfiguration Cost for Reconfigurable Computing Architectures. | Shigeyuki Takano, Hideharu Amano |
| 2021 | ASPDAC | TCI Tester: Tester for Through Chip Interface. | Hideto Kayashima, Hideharu Amano |
| 2021 | PDP | A Case for Low-Latency Network-on-Chip using Compression Routers. | Naoya Niwa, Yoshiya Shikama, Hideharu Amano, Michihiro Koibuchi |
| 2021 | PDP | Low-Latency Low-Energy Memory-Cube Networks using Dual-Voltage Datapaths. | Yoshiya Shikama, Ryuta Kawano, Hiroki Matsutani, Hideharu Amano, Yusuke Nagasaka, Naoto Fukumoto, Michihiro Koibuchi |
| 2020 | PDP | Accelerating Deep Learning using Multiple GPUs and FPGA-Based 10GbE Switch. | Tomoya Itsubo, Michihiro Koibuchi, Hideharu Amano, Hiroki Matsutani |
| 2019 | DAC | Sparse 3-D NoCs with Inductive Coupling. | Michihiro Koibuchi, Lambert T. Leong, Tomohiro Totoki, Naoya Niwa, Hiroki Matsutani, Hideharu Amano, Henri Casanova |
| 2019 | FPL | Demonstration of Flow-in-Cloud: A Multi-FPGA System. | Kazuei Hironaka, Kensuke Iizuka, Akram Ben Ahmed, M. M. Imdad Ullah, Yugo Yamauchi, Yuxi Sun, Miho Yamakura, Aoi Hiruma, Hideharu Amano |
| 2019 | FPL | Demonstration of Low Power Stream Processing Using a Variable Pipelined CGRA. | Takuya Kojima, Naoki Ando, Yusuke Matsushita, Hideharu Amano |
| 2019 | SNPD | Multi-FPGA Management on Flow-in-Cloud Prototype System. | Kazuei Hironaka, Akram Ben Ahmed, Hideharu Amano |
| 2018 | DDECS | Superpixel Accelerator for Computer Vision Applications on Arria 10 SoC. | Amila Akagic, Emir Buza, Razija Turcinhodzic, Hana Haseljic, Hiroyuki Noda, Hideharu Amano |
| 2018 | FCCM | Performance Prediction for Large-Scale Heterogeneous Platforms. | Ryota Yasudo, Ana Lucia Varbanescu, Jos Gabriel F. Coutinho, Wayne Luk, Hideharu Amano |
| 2018 | FPL | A Configuration Data Multicasting Method for Coarse-Grained Reconfigurable Architectures. | Takuya Kojima, Hideharu Amano |
| 2017 | CLUSTER | A Case for Uni-directional Network Topologies in Large-Scale Clusters. | Michihiro Koibuchi, Tomohiro Totoki, Hiroki Matsutani, Hideharu Amano, Fabien Chaix, Ikki Fujiwara, Henri Casanova |
| 2017 | FPL | Body bias optimization for variable pipelined CGRA. | Takuya Kojima, Naoki Ando, Hayate Okuhara, Ng. Anh Vu Doan, Hideharu Amano |
| 2017 | FPL | In-switch approximate processing: Delayed tasks management for MapReduce applications. | Koya Mitsuzuka, Ami Hayashi, Michihiro Koibuchi, Hideharu Amano, Hiroki Matsutani |
| 2017 | FPL | Accelerator-in-switch: A framework for tightly coupled switching hub and an accelerator with FPGA. | Chiharu Tsuruta, Takahiro Kaneda, Naoki Nishikawa, Hideharu Amano |
| 2017 | HPCA | High-Bandwidth Low-Latency Approximate Interconnection Networks. | Daichi Fujiki, Kiyo Ishii, Ikki Fujiwara, Hiroki Matsutani, Hideharu Amano, Henri Casanova, Michihiro Koibuchi |
| 2017 | ICPADS | HiRy: An Advanced Theory on Design of Deadlock-Free Adaptive Routing for Arbitrary Topologies. | Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano |
| 2017 | ICPP | Order/Radix Problem: Towards Low End-to-End Latency Interconnection Networks. | Ryota Yasudo, Michihiro Koibuchi, Koji Nakano, Hiroki Matsutani, Hideharu Amano |
| 2017 | NSS | Implementation of Bitsliced AES Encryption on CUDA-Enabled GPU. | Naoki Nishikawa, Hideharu Amano, Keisuke Iwai |
| 2016 | DAC | Leveraging FDSOI through body bias domain partitioning and bias search. | Johannes Maximilian Khn, Hideharu Amano, Oliver Bringmann, Wolfgang Rosenstiel |
| 2016 | FPL | Body bias grain size exploration for a coarse grained reconfigurable accelerator. | Yusuke Matsushita, Hayate Okuhara, Koichiro Masuyama, Yu Fujita, Ryuta Kawano, Hideharu Amano |
| 2016 | PDP | Randomizing Packet Memory Networks for Low-Latency Processor-Memory Communication. | Daichi Fujiki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano |
| 2015 | DATE | Spatial and temporal granularity limits of body biasing in UTBB-FDSOI. | Johannes Maximilian Khn, Dustin Peterson, Hideharu Amano, Oliver Bringmann, Wolfgang Rosenstiel |
| 2015 | FPL | Reduction calculator in an FPGA based switching Hub for high performance clusters. | Takuya Kuhara, Chiharu Tsuruta, Toshihiro Hanawa, Hideharu Amano |
| 2015 | FPL | Significant papers from the first 25 years of the FPL conference. | Philip Heng Wai Leong, Hideharu Amano, Jason Helge Anderson, Koen Bertels, Joo M. P. Cardoso, Oliver Diessel, Guy Gogniat, Mike Hutton, JunKyu Lee, Wayne Luk, Patrick Lysaght, Marco Platzner, Viktor K. Prasanna, Tero Rissa, Cristina Silvano, Hayden Kwok-Hay So, Yu Wang |
| 2015 | FPL | 7MOPS/lemon-battery image processing demonstration with an ultra-low power reconfigurable accelerator CMA-SOTB-2. | Koichiro Masuyama, Yu Fujita, Hayate Okuhara, Hideharu Amano |
| 2015 | ISLPED | An optimal power supply and body bias voltage for a ultra low power micro-controller with silicon on thin box MOSFET. | Hayate Okuhara, Kuniaki Kitamori, Yu Fujita, Kimiyoshi Usami, Hideharu Amano |
| 2015 | PDP | Optimized Core-Links for Low-Latency NoCs. | Ryuta Kawano, Seiichi Tade, Ikki Fujiwara, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi |
| 2014 | ASPDAC | Design and control methodology for fine grain power gating based on energy characterization and code profiling of microprocessors. | Kimiyoshi Usami, Masaru Kudo, Kensaku Matsunaga, Tsubasa Kosaka, Yoshihiro Tsurui, Weihan Wang, Hideharu Amano, Hiroaki Kobayashi, Ryuichi Sakamoto, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura |
| 2014 | DATE | Design and evaluation of fine-grained power-gating for embedded microprocessors. | Masaaki Kondo, Hiroaki Kobayashi, Ryuichi Sakamoto, Motoki Wada, Jun Tsukamoto, Mitaro Namiki, Weihan Wang, Hideharu Amano, Kensaku Matsunaga, Masaru Kudo, Kimiyoshi Usami, Toshiya Komoda, Hiroshi Nakamura |
| 2014 | DATE | Low-latency wireless 3D NoCs via randomized shortcut chips. | Hiroki Matsutani, Michihiro Koibuchi, Ikki Fujiwara, Takahiro Kagami, Yasuhiro Take, Tadahiro Kuroda, Paul Bogdan, Radu Marculescu, Hideharu Amano |
| 2014 | FPL | A high speed design and implementation of dynamically reconfigurable processor using 28NM SOI technology. | Toru Katagiri, Hideharu Amano |
| 2014 | FPL | Body bias control for a coarse grained reconfigurable accelerator implemented with Silicon on Thin BOX technology. | Honlian Su, Yu Fujita, Hideharu Amano |
| 2013 | AINA | A Circuit Division Method for High-Level Synthesis on Multi-FPGA Systems. | Kugami Daiki, Takaaki Miyajima, Hideharu Amano |
| 2013 | AINA | An FPGA Implementation of Reconfigurable Real-Time Vision Architecture. | Jorge Hiraiwa, Hideharu Amano |
| 2013 | AINA | Research of PE Array Connection Network for Cool Mega-Array. | Rie Uno, Nobuaki Ozaki, Hideharu Amano |
| 2013 | ASPDAC | A case for wireless 3D NoCs for CMPs. | Hiroki Matsutani, Paul Bogdan, Radu Marculescu, Yasuhiro Take, Daisuke Sasaki, Hao Zhang, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano |
| 2013 | FPL | Demonstration of a heterogeneous multi-core processor with 3-D inductive coupling links. | Yusuke Koizumi, Noriyuki Miura, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura |
| 2013 | FPL | A fully pipelined FPGA architecture for stochastic simulation of chemical systems. | David B. Thomas, Hideharu Amano |
| 2013 | FPL | A hardware complete detection mechanism for an energy efficient reconfigurable accelerator CMA. | Akihito Tsusaka, Mai Izawa, Rie Uno, Nobuyuki Ozaki, Hideharu Amano |
| 2013 | ICA3PP | A Routing Strategy for Inductive-Coupling Based Wireless 3-D NoCs by Maximizing Topological Regularity. | Daisuke Sasaki, Hao Zhang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano |
| 2012 | ASPDAC | A multi-Vdd dynamic variable-pipeline on-chip router for CMPs. | Hiroki Matsutani, Yuto Hirata, Michihiro Koibuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano |
| 2012 | FPL | Performance analysis of fully-adaptable CRC accelerators on an FPGA. | Amila Akagic, Hideharu Amano |
| 2012 | FPL | Reconfigurable out-of-order mechanism generator for unstructured grid computation in computational fluid dynamics. | Takayuki Akamine, Kenta Inakagata, Yasunori Osana, Naoyuki Fujita, Hideharu Amano |
| 2012 | FPL | CMA-Cube: A scalable reconfigurable accelerator with 3-D wireless inductive coupling interconnect. | Yusuke Koizumi, Eiichi Sasaki, Hideharu Amano, Hiroki Matsutani, Yasuhiro Take, Tadahiro Kuroda, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura |
| 2012 | ISCA | A case for random shortcut topologies for HPC interconnects. | Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, D. Frank Hsu, Henri Casanova |
| 2012 | RTCSA | An OpenCL Runtime Library for Embedded Multi-Core Accelerator. | Ryuichi Sakamoto, Mikiko Sato, Yusuke Koizumi, Hideharu Amano, Mitaro Namiki |
| 2011 | ASPDAC | Geyser-2: The second prototype CPU with fine-grained run-time power gating. | Lei Zhao, Daisuke Ikebuchi, Yoshiki Saito, M. Kamata, Naomi Seki, Yu Kojima, Hideharu Amano, Satoshi Koyama, Tatsunori Hashida, Y. Umahashi, D. Masuda, Kimiyoshi Usami, Keiji Kimura, Mitaro Namiki, Seidai Takeda, Hiroshi Nakamura, Masaaki Kondo |
| 2011 | ISLPED | On-chip detection methodology for break-even time of power gated function units. | Kimiyoshi Usami, Yuya Goto, Kensaku Matsunaga, Satoshi Koyama, Daisuke Ikebuchi, Hideharu Amano, Hiroshi Nakamura |
| 2011 | RTCSA | A Dynamic Link-Width Optimization for Network-on-Chip. | Daihan Wang, Michihiro Koibuchi, Tomohiro Yoneda, Hiroki Matsutani, Hideharu Amano |
| 2010 | ASPDAC | Geyser-1: a MIPS R3000 CPU core with fine-grained run-time power gating. | Daisuke Ikebuchi, Naomi Seki, Yu Kojima, M. Kamata, Lei Zhao, Hideharu Amano, Toshiaki Shirai, Satoshi Koyama, Tatsunori Hashida, Y. Umahashi, Hiroki Masuda, Kimiyoshi Usami, Seidai Takeda, Hiroshi Nakamura, Mitaro Namiki, Masaaki Kondo |
| 2010 | ASPDAC | MuCCRA-3: a low power dynamically reconfigurable processor array. | Yoshiki Saito, Toru Sano, Masaru Kato, Vasutan Tunbunheng, Yoshihiro Yasuda, Masayuki Kimura, Hideharu Amano |
| 2010 | MICRO | A variable-pipeline on-chip router optimized to traffic pattern. | Yuto Hirata, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano |
| 2009 | FPL | Modularizing flux limiter functions for a Computational Fluid Dynamics accelerator on FPGAs. | Kenta Inakagata, Hirokazu Morishita, Yasunori Osana, Naoyuki Fujita, Hideharu Amano |
| 2009 | FPL | Configuring area and performance: Empirical evaluation on an FPGA-based biochemical simulator. | Tomonori Ooya, Hideki Yamada, Tomoya Ishimori, Yuichiro Shibata, Yasunori Osana, Kiyoshi Oguri, Masato Yoshimi, Yuri Nishikawa, Akira Funahashi, Noriko Hiroi, Hideharu Amano |
| 2009 | FPL | MuCCRA-Cube: A 3D dynamically reconfigurable processor with inductive-coupling link. | Shotaro Saito, Yoshinori Kohama, Yasufumi Sugimori, Yohei Hasegawa, Hiroki Matsutani, Toru Sano, Kazutaka Kasuga, Yoichi Yoshida, Kiichi Niitsu, Noriyuki Miura, Tadahiro Kuroda, Hideharu Amano |
| 2009 | FPL | Fine Grain Partial Reconfiguration for energy saving in Dynamically Reconfigurable Processors. | Toru Sano, Yoshiki Saito, Masaru Kato, Hideharu Amano |
| 2009 | HPCA | Prediction router: Yet another low latency on-chip router architecture. | Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tsutomu Yoshinaga |
| 2009 | ISPA | Performance Analysis of ClearSpeed's CSX600 Interconnects. | Yuri Nishikawa, Michihiro Koibuchi, Masato Yoshimi, Akihiro Shitara, Kenichi Miura, Hideharu Amano |
| 2009 | PDPTA | An On/Off Link Activation Method for Power Regulation in InfiniBand. | Jos Miguel Montaana Aliaga, Michihiro Koibuchi, Takafumi Watanabe, Tomoyuki Hiroyasu, Hiroki Matsutani, Hideharu Amano |
| 2009 | VLSID | Design and Implementation of Fine-Grain Power Gating with Ground Bounce Suppression. | Kimiyoshi Usami, Toshiaki Shirai, Tatsunori Hashida, Hiroki Masuda, Seidai Takeda, Mitsutaka Nakata, Naomi Seki, Hideharu Amano, Mitaro Namiki, Masashi Imai, Masaaki Kondo, Hiroshi Nakamura |
| 2008 | ASPDAC | Run-time power gating of on-chip routers using look-ahead routing. | Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Daihan Wang |
| 2008 | FPL | Power reduction techniques for Dynamically Reconfigurable Processor Arrays. | Takashi Nishimura, Keiichiro Hirai, Yoshiki Saito, Takuro Nakamura, Yohei Hasegawa, Satoshi Tsutsumi, Vasutan Tunbunheng, Hideharu Amano |
| 2008 | FPL | Instruction buffer mode for multi-context Dynamically Reconfigurable Processors. | Toru Sano, Masaru Kato, Satoshi Tsutsumi, Yohei Hasegawa, Hideharu Amano |
| 2008 | FPL | A link removal methodology for Networks-on-Chip on reconfigurable systems. | Daihan Wang, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi |
| 2008 | FPL | Practical implementation of a network-based stochastic biochemical simulation system on an FPGA. | Masato Yoshimi, Yuri Nishikawa, Yasunori Osana, Akira Funahashi, Yuichiro Shibata, Hideki Yamada, Noriko Hiroi, Hiroaki Kitano, Hideharu Amano |
| 2008 | ICCD | A fine-grain dynamic sleep control scheme in MIPS R3000. | Naomi Seki, Lei Zhao, Jo Kei, Daisuke Ikebuchi, Yu Kojima, Yohei Hasegawa, Hideharu Amano, Toshihiro Kashima, Seidai Takeda, Toshiaki Shirai, Mitsutaka Nakata, Kimiyoshi Usami, Tetsuya Sunata, Jun Kanai, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura |
| 2007 | FPL | Design Methodology and Trade-offs Analysis for Parameterized Dynamically Reconfigurable Processor Arrays. | Yohei Hasegawa, Hideharu Amano |
| 2007 | FPL | A High Speed License Plate Recognition System on an FPGA. | Takamasa Kanamori, Hideharu Amano, Masatoshi Arai, Daisuke Konno, Tomomichi Nanba, Yoshiaki Ajioka |
| 2007 | FPL | A Temporal Correlation Based Port Combination Methodology for Networks-on-chip on Reconfigurable Systems. | Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano |
| 2007 | FPL | A Combining technique of rate law functions for a cost-effective reconfigurable biological simulator. | Hideki Yamada, Naoki Iwanaga, Yuichiro Shibata, Yasunori Osana, Masato Yoshimi, Yow Iwaoka, Yuri Nishikawa, Toshinori Kojima, Hideharu Amano, Akira Funahashi, Noriko Hiroi, Hiroaki Kitano, Kiyoshi Oguri |
| 2007 | FPL | FPGA Implementation of a Data-Driven Stochastic Biochemical Simulator with the Next Reaction Method. | Masato Yoshimi, Yow Iwaoka, Yuri Nishikawa, Toshinori Kojima, Yasunori Osana, Akira Funahashi, Noriko Hiroi, Yuichiro Shibata, Naoki Iwanaga, Hideki Yamada, Hiroaki Kitano, Hideharu Amano |
| 2007 | ICPP | Tightly-Coupled Multi-Layer Topologies for 3-D NoCs. | Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano |
| 2007 | ICPP | Performance Improvement Methodology for ClearSpeed's CSX600. | Yuri Nishikawa, Michihiro Koibuchi, Masato Yoshimi, Kenichi Miura, Hideharu Amano |
| 2007 | PDPTA | Implementation and Evaluation of Multicast Mechanism on Network Interface Plugged into a Memory Slot. | Atsushi Ohta, Yoshihiro Hamada, Akira Kitamura, Noboru Tanabe, Hideharu Amano, Hironori Nakajo |
| 2006 | FPL | A Context Dependent Clock Control Mechanism for Dynamically Reconfigurable Processors. | Hideharu Amano, Yohei Hasegawa, Shohei Abe, Kenichiro Ishikawa, Shunsuke Tsutsumi, Shunsuke Kurotaki, Takuro Nakamura, Takashi Nishimura |
| 2006 | FPL | Performance Evaluation of an Fpga-Based Biochemical Simulator ReCSip. | Yasunori Osana, Masato Yoshimi, Akira Funahashi, Noriko Hiroi, Yuichiro Shibata, Naoki Iwanaga, Hiroaki Kitano, Hideharu Amano |
| 2006 | FPL | An FPGA Implementation of High Throughput Stochastic Simulator for Large-Scale Biochemical Systems. | Masato Yoshimi, Yasunori Osana, Yow Iwaoka, Yuri Nishikawa, Toshinori Kojima, Akira Funahashi, Noriko Hiroi, Yuichiro Shibata, Naoki Iwanaga, Hiroaki Kitano, Hideharu Amano |
| 2006 | ICPP | Switch-tagged VLAN Routing Methodology for PC Clusters with Ethernet. | Tomohiro Otsuka, Michihiro Koibuchi, Tomohiro Kudoh, Hideharu Amano |
| 2006 | ISPA | Enforcing Dimension-Order Routing in On-Chip Torus Networks Without Virtual Channels. | Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano |
| 2005 | FCCM | Performance and Cost Analysis of Time-Multiplexed Execution on the Dynamically Reconfigurable Processor. | Hideharu Amano, Shohei Abe, Yohei Hasegawa, Katsuaki Deguchi, Masayasu Suzuki |
| 2005 | FPGA | Time-multiplexed execution on the dynamically reconfigurable processor: a performance/cost evaluation. | Yohei Hasegawa, Shohei Abe, Katsuaki Deguchi, Masayasu Suzuki, Hideharu Amano |
| 2005 | FPL | An I/O mechanism on a Dynamically Reconfigurable Processor - Which should be moved: Data or Configuration? | Hideharu Amano, Shohei Abe, Katsuaki Deguchi, Yohei Hasegawa |
| 2005 | FPL | Efficient Scheduling of Rate Law Functions for ODE-Based Multimodel Biochemical Simulation on an FPGA. | Naoki Iwanaga, Yuichiro Shibata, Masato Yoshimi, Yasunori Osana, Yow Iwaoka, Tomonori Fukushima, Hideharu Amano, Akira Funahashi, Noriko Hiroi, Hiroaki Kitano, Kiyoshi Oguri |
| 2005 | FPL | A Framework for ODE-Based Multimodel Biochemical Simulations on an FPGA. | Yasunori Osana, Yow Iwaoka, Tomonori Fukushima, Masato Yoshimi, Akira Funahashi, Noriko Hiroi, Yuichiro Shibata, Naoki Iwanaga, Hiroaki Kitano, Hideharu Amano |
| 2005 | ICPP | VLAN-Based Minimal Paths in PC Cluster with Ethernet on Mesh and Torus. | Tomohiro Otsuka, Michihiro Koibuchi, Akiya Jouraku, Hideharu Amano |
| 2005 | IROS | Implementation of active direction-pass filter on dynamically reconfigurable processor. | Shunsuke Kurotaki, Noriaki Suzuki, Kazuhiro Nakadai, Hiroshi G. Okuno, Hideharu Amano |
| 2005 | PDCAT | Evaluation of Network Interface Controller on DIMMnet-2 Prototype Board. | Akira Kitamura, Yasuo Miyabe, Tetsu Izawa, Tomotaka Miyashiro, Konosuke Watanabe, Tomohiro Otsuka, Hideharu Amano, Yoshihiro Hamada, Noboru Tanabe, Hironori Nakajo |
| 2005 | PDPTA | A Packet Forwarding Layer for DIMMnet and its Hardware Implementation. | Yoshihiro Hamada, Hiroaki Nishi, Akira Kitamura, Noboru Tanabe, Hideharu Amano, Hironori Nakajo |
| 2005 | PDPTA | Implementation of ISIS-SimpleScalar. | Toshihiro Hanawa, Toshiya Minai, Yasuki Tanabe, Hideharu Amano |
| 2005 | PDPTA | Destination Bundle: A Routing Table Reduction Technique for Distributed Routing on Dependable Networks-on-Chips. | Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano |
| 2004 | ASPDAC | Future reconfigurable computing system. | Masahiko Kawamura, Hideharu Amano |
| 2004 | ASPDAC | ReCSiP: a reconfigurable cell simulation platform: accelerating biological applications with FPGA. | Yasunori Osana, Tomonori Fukushima, Hideharu Amano |
| 2004 | EUC | Folded Fat H-Tree: An Interconnection Topology for Dynamically Reconfigurable Processor Array. | Yutaka Yamada, Hideharu Amano, Michihiro Koibuchi, Akiya Jouraku, Kenichiro Anjo, Katsunobu Nishimura |
| 2004 | FCCM | Implementing and Evaluating Stream Applications on the Dynamically Reconfigurable Processor. | Noriaki Suzuki, Shunsuke Kurotaki, Masayasu Suzuki, Naoto Kaneko, Yutaka Yamada, Katsuaki Deguchi, Yohei Hasegawa, Hideharu Amano, Kenichiro Anjo, Masato Motomura, Kazutoshi Wakabayashi, Takeo Toi, Toru Awashima |
| 2004 | FPL | Techniques for Virtual Hardware on a Dynamically Reconfigurable Processor - An Approach to Tough Cases. | Hideharu Amano, Takeshi Inuo, Hirokazu Kami, Taro Fujii, Masayasu Suzuki |
| 2004 | FPL | Stochastic Simulation for Biochemical Reactions on FPGA. | Masato Yoshimi, Yasunori Osana, Tomonori Fukushima, Hideharu Amano |
| 2003 | ASPDAC | MAPLE chip: a processing element for a static scheduling centric multiprocessor. | Kenta Yasufuku, Riku Ogawa, Keisuke Iwai, Hideharu Amano |
| 2003 | CCGRID | Performance Evaluation of RHiNET-2/NI: A Network Interface for Distributed Parallel Computing Systems. | Konosuke Watanabe, Tomohiro Otsuka, Junichiro Tsuchiya, Hideharu Amano, Hiroshi Harada, Junji Yamamoto, Hiroaki Nishi, Tomohiro Kudoh |
| 2003 | CLUSTER | Performance Evaluation of Routing Algorithms in RHiNET-2 Cluster. | Michihiro Koibuchi, Konosuke Watanabe, Kenichi Kono, Akiya Jouraku, Hideharu Amano |
| 2003 | FPL | A Dynamically Adaptive Switching Fabric on a Multicontext Reconfigurable Device. | Hideharu Amano, Akiya Jouraku, Kenichiro Anjo |
| 2003 | FPL | Reducing the Configuration Loading Time of a Coarse Grain Multicontext Reconfigurable Device. | Toshiro Kitaoka, Hideharu Amano, Kenichiro Anjo |
| 2003 | FPL | Implementation of ReCSiP: A ReConfigurable Cell SImulation Platform. | Yasunori Osana, Tomonori Fukushima, Hideharu Amano |
| 2003 | ICPP | Descending Layers Routing: A Deadlock-Free Deterministic Routing using Virtual Channels in System Area Networks with Irregular Topologies. | Michihiro Koibuchi, Akiya Jouraku, Konosuke Watanabe, Hideharu Amano |
| 2003 | PDPTA | Performance Evaluation of Instruction Set Architecture of MBP-Light: A Distributed Memory Controller for a Large Scale Multiprocessor. | Noriaki Suzuki, Hideharu Amano |
| 2003 | PDPTA | Performance Evaluation of 3-Dimensional MIN with Cache Consistency Maintenance Mechanism. | Yasuki Tanabe, Takashi Midorikawa, Daisuke Shiraishi, Masayoshi Shigeno, Toshihiro Hanawa, Hideharu Amano |
| 2002 | FPL | RHiNET/NI: A Reconfigurable Network Interface for Cluster Computing. | Naoyuki Izu, Tomonori Yokoyama, Junichiro Tsuchiya, Konosuke Watanabe, Hideharu Amano |
| 2002 | FPL | A General Hardware Design Model for Multicontext FPGAs. | Naoto Kaneko, Hideharu Amano |
| 2002 | PDPTA | The Impact of Path Selection Algorithm of Adaptive Routing for Implementing Deterministic Routing. | Michihiro Koibuchi, Akiya Jouraku, Hideharu Amano |
| 2001 | ASPDAC | A prototype chip of multicontext FPGA with DRAM for virtual hardware. | Daisuke Kawakami, Yuichiro Shibata, Hideharu Amano |
| 2001 | CATA | The impact of output selection function on adaptive routing. | Akira Funahashi, Michihiro Koibuchi, Akiya Jouraku, Hideharu Amano |
| 2001 | HOTI | RHiNET-3/SW: an 80-Gbit/s high-speed network switch for distributed parallel computing. | Shinji Nishimura, Tomohiro Kudoh, Hiroaki Nishi, Junji Yamamoto, Ryuichiro Ueno, Katsuyoshi Harasawa, Shuji Fukuda, Yasutaka Shikichi, Shigeto Akutsu, Koji Tasho, Hideharu Amano |
| 2001 | ICPP | L-Turn Routing: An Adaptive Routing in Irregular Networks. | Michihiro Koibuchi, Akira Funahashi, Akiya Jouraku, Hideharu Amano |
| 2000 | ASPDAC | A floating point arithmetic unit for a static scheduling and compiler oriented multiprocessor system. | Takahiro Kawaguchi, Takayuki Suzuki, Hideharu Amano |
| 2000 | CLUSTER | MEMOnet : Network interface plugged into a memory slot. | Noboru Tanabe, Junji Yamamoto, Hiroaki Nishi, Tomohiro Kudoh, Yoshihiro Hamada, Hironori Nakajo, Hideharu Amano |
| 2000 | FCCM | A Virtual Hardware System on a Dynamically Reconfigurable Logic Device. | Yuichiro Shibata, Masaki Uno, Hideharu Amano, Koichiro Furuta, Taro Fujii, Masato Motomura |
| 2000 | FCCM | A Reconfigurable Stochastic Model Simulator for Analysis of Parallel Systems. | Ou Yamamoto, Yuichiro Shibata, Hitoshi Kurosawa, Hideharu Amano |
| 2000 | FPL | Reconfigurable Systems: New Activities in Asia. | Hideharu Amano, Yuichiro Shibata, Masaki Uno |
| 2000 | FPL | Dataflow Partitioning and Scheduling Algorithms for WASMII, a Virtual Hardware. | Atsushi Takayama, Yuichiro Shibata, Keisuke Iwai, Hideharu Amano |
| 2000 | FPL | A Reconfigurable Stochastic Model Simulator for Analysis of Parallel Systems. | Ou Yamamoto, Yuichiro Shibata, Hitoshi Kurosawa, Hideharu Amano |
| 2000 | HPDC | A Local Area System Network RHinet-1: A Network for High Performance Parallel Computing. | Hiroaki Nishi, Koji Tasho, Junji Yamamoto, Tomohiro Kudoh, Hideharu Amano |
| 2000 | PDPTA | Coherence Protocol for Home Proxy Cache on RHiNET. | Hironori Nakajo, M. Ishii, T. Kudo, Hideharu Amano |
| 1998 | ASPDAC | Reconfigurable Systems: Activities in Asia and South Pacific (Embedded Tutorial). | Hideharu Amano, Yuichiro Shibata |
| 1998 | ASPDAC | The MINC (Multistage Interconnection Network with Cache Control Mechanism) Chip. | Takashi Midorikawa, Takayuki Kamei, Toshihiro Hanawa, Hideharu Amano |
| 1997 | ASPDAC | An LSI implementation of the simple serial synchronized multistage interconnection network. | Takayuki Kamei, Masashi Sasahara, Hideharu Amano |
| 1997 | ASPDAC | The RDT network router chip. | Hiroaki Nishi, Hideharu Amano, Katsunobu Nishimura, Kenichiro Anjo, Tomohiro Kudoh |
| 1997 | EuroPar | Shared vs. Snoop: Evaluation of Cache Structure for Single-Chip Multiprocessors. | Toru Kisuki, Masaki Wakabayashi, Junji Yamamoto, Keisuke Inoue, Hideharu Amano |
| 1997 | FPL | A reconfigurable sensor-data processing system for personal robots. | Kazumasa Nukata, Yuichiro Shibata, Hideharu Amano, Yuichiro Anzai |
| 1997 | PDPTA | Total System Image of the Reconfigurable Machine WASMII. | Xiao-ping Ling, Yuichiro Shibata, Hidenori Miyazaki, Hideharu Amano, Koichi Higure |
| 1996 | FPL | ATTEMPT-1: A Reconfigurable Multiprocessor Testbed. | Keisuke Inoue, Toru Kisuki, Michitaka Okuno, Etsuko Shimizu, Takuya Terasawa, Hideharu Amano |
| 1996 | FPL | An Emulation System of the WASMII: A Data Driven Computer on a Virtual Hardware. | Yuichiro Shibata, Xiao-ping Ling, Hideharu Amano |
| 1995 | ICPP | Hierarchical Bit-Map Directory Schemes on the RDT Interconnection Network for a Massively Parallel Processor JUMP-1. | Tomohiro Kudoh, Hideharu Amano, Takashi Matsumoto, Kei Hiraki, Yulu Yang, Katsunobu Nishimura, Koichi Yoshimura, Yasuhito Fukushima |
| 1994 | FPL | Software Environment for WASMII: a Data Driven Machine with a Virtual Hardware. | Xiao-yu Chen, Xiao-ping Ling, Hideharu Amano |
| 1994 | ICPP | Multistage Interconnection Networks with Multiple Outlets. | Toshihiro Hanawa, Hideharu Amano, Yoshifumi Fujikawa |
| 1994 | ICPP | SNAIL: A Multiprocessor Based on the Simple Serial Synchronized Multistage Interconnection Network Architecture. | Masashi Sasahara, Jun Terada, Luo Zhou, Kalidou Gaye, Jun-ichi Yamato, Satoshi Ogura, Hideharu Amano |
| 1992 | ICPP | A Parallel Logic Simulation Algorithm Based on Query. | Tomohiro Kudoh, Tetsuro Kimura, Hideharu Amano, Takuya Terasawa |
| 1991 | ICPP | A Batcher Double Omega Network with Combining. | Hideharu Amano, Kalidou Gaye |
| 1990 | ICPP | A Fault Tolerant Batcher Network. | Hideharu Amano |
| 1988 | ISCA | IMPULSE: A High Performance Processing Unit for Multiprocessors for Scientific Calculation. | Taisuke Boku, Shigehiro Nomura, Hideharu Amano |
| 1985 | ISCA | (SM)²-II: A New Version of the Sparse Matrix Solving Machine. | Hideharu Amano, Taisuke Boku, Tomohiro Kudoh, Hideo Aiso |
| 1983 | ISCA | (SM)2: Sparse Matrix Solving Machine | Hideharu Amano, Takaichi Yoshida, Hideo Aiso |