| 2025 | Reducing FPGA Placement Runtime by Clustering of Netlist Blocks. | Markus Rein, Dirk Stroobandt |
| 2025 | Double Duty: FPGA Architecture to Enable Concurrent LUT and Adder Chain Usage. | Junius Pun, Xilai Dai, Grace Zgheib, Mahesh A. Iyer, Andrew Boutros, Vaughn Betz, Mohamed S. Abdelfattah |
| 2025 | Towards Instruction-Controlled In-Pipeline GEMM Acceleration in a Dual-Issue RISC-V Core for Edge Applications. | Ahmad Othman, Darmen Ilyas, Ahmed Kamaleldin, Diana Ghringer |
| 2025 | Performance Impact on Reducing Energy Consumption Applying Adaptive Stream-Based Entropy Coding on FPGA. | Taku Nishikawa, Koichi Marumo, Shinichi Yamagiwa |
| 2025 | Routino: Accelerating FPGA Routing Through Efficient Memory Representation. | Davide Nicolini, Corrado De Sio, Eleonora Vacca, Luca Sterpone |
| 2025 | GAMA: High-Performance GEMM Acceleration on AMD Versal ML-Optimized AI Engines. | Kaustubh Manohar Mhatre, Endri Taka, Aman Arora |
| 2025 | Cocotb-Pynq: Co-Simulating Python+RTL Applications Targeting Pynq Platforms with Cocotb. | Gavin Lusby, Nachiket Kapre |
| 2025 | TRPlaceFPGA-MP: A Two-Stage Reinforcement Learning Framework for Fast FPGA Macro Placer. | Qin Luo, Xinshi Zang, Evangeline F. Y. Young, Martin D. F. Wong |
| 2025 | AMD Versal Implementations of FAM and SSCA Estimators. | Carol Jingyi Li, Ruilin Wu, Philip H. W. Leong |
| 2025 | Maximum FPGA: A 32K-Point 32-Parallel Floating Point FFT. | Martin Langhammer, Bogdan Pasca |
| 2025 | FPGAs with FABulous - Framework and Chips. | Dirk Koch, Myrtle Shah, King Lok Chung, Jonas Kuenstler, Marcel Jung, Jakob Ternes, Asma Mohsin, Gennadiy Knis |
| 2025 | FINN-GL: Generalized Mixed-Precision Extensions for FPGA-Accelerated LSTMS. | Shashwat Khandelwal, Jakoba Petri-Koenig, Thomas B. Preuer, Michaela Blott, Shanker Shreejith |
| 2025 | NeuGEMM: A Reordering-Free Unified GEMM-Conv2D Accelerator for Lightweight Neuromorphic Processors. | Hyeonguk Jang, Sukho Lee, Jae-Jin Lee, Kyuseung Han |
| 2025 | Hybrid Weightless Neural Networks for Efficient Edge Inference. | Mugdha P. Jadhao, Alan T. L. Bacellar, Shashank Nag, Igor D. S. Miranda, Felipe M. G. Frana, Lizy K. John |
| 2025 | Virtualization and Dynamic Reconfiguration of Custom Instruction Accelerators (CIA) in RISC-V Embedded Systems. | Bea Healy, Brandon Freiberger, Jonas Kuenstler, King Lok Chung, Emil Cozac, Meinhard Kissich, Gennadiy Knis, Ron Sass, Dirk Koch, Jan Gray, Guy Lemieux |
| 2025 | Accelerating Transposed Convolutions on FPGA-Based Edge Devices. | Jude Haris, Jos Cano |
| 2025 | NPX: Automating Neuromorphic Processor Design from Spike-Based Learning to FPGA Prototyping. | Kyuseung Han, Hyeonguk Jang, Sukho Lee, Sung-Eun Kim, Kyudong Hwang, Jae-Jin Lee |
| 2025 | Using Data to Reduce Uncertainty in FPGA Routing. | Andrew David Gunter, Steven J. E. Wilton |
| 2025 | Versatile Place and Route with Continuous Routing Runtime Prediction and Smart Route Termination. | Andrew David Gunter, Steven J. E. Wilton |
| 2025 | Open-Source FPGA Routing Runtime Prediction for Improved Productivity Via Smart Route Termination. | Andrew David Gunter, Steven J. E. Wilton |
| 2025 | Compile in Seconds and Run on an FPGA with DynaRapid. | Andrea Guerrieri, Isaac John Wetenkamp, Chris Lavin, Eddie Hung, Lana Josipovic, Paolo Ienne |
| 2025 | Improving Boolean Satisfiability-Based Modulo Scheduling. | Nicolai Fiege, Peter Zipf |
| 2025 | Multiplexer Optimizations for Virtex FPGAs. | Nicolai Fiege, Martin Hardieck, Peter Zipf |
| 2025 | Energy-Efficient DNNs on FPGAs for Edge-Cloud Computer Vision. | Qaisar Farooq, Idilio Drago |
| 2025 | From Errors to Solutions: LLM-Powered Command Scripting for FPGA Cad Tools. | Mohamed A. Elgammal, Vaughn Betz |