| 2022 | FPGA | Logic Shrinkage: Learned FPGA Netlist Sparsity for Efficient Neural Network Inference. | Erwei Wang, James J. Davis, Georgios-Ilias Stavrou, Peter Y. K. Cheung, George A. Constantinides, Mohamed S. Abdelfattah |
| 2021 | Mobisys | Enabling Binary Neural Network Training on the Edge. | Erwei Wang, James J. Davis, Daniele Moro, Piotr Zielinski, Jia Jie Lim, Claudionor Coelho, Satrajit Chatterjee, Peter Y. K. Cheung, George A. Constantinides |
| 2019 | FCCM | LUTNet: Rethinking Inference in FPGA Soft Logic. | Erwei Wang, James J. Davis, Peter Y. K. Cheung, George A. Constantinides |
| 2019 | FPL | Accelerating Position-Aware Top-k ListNet for Ranking Under Custom Precision Regimes. | Qiang Li, Erwei Wang, Shane T. Fleming, David B. Thomas, Peter Y. K. Cheung |
| 2018 | FCCM | A PYNQ-Based Framework for Rapid CNN Prototyping. | Erwei Wang, James J. Davis, Peter Y. K. Cheung |
| 2017 | FPL | STRIPE: Signal selection for runtime power estimation. | James J. Davis, Joshua M. Levine, Edward A. Stott, Eddie Hung, Peter Y. K. Cheung, George A. Constantinides |
| 2016 | FCCM | KAPow: A System Identification Approach to Online Per-Module Power Estimation in FPGA Designs. | Eddie Hung, James J. Davis, Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung, George A. Constantinides |
| 2016 | FCCM | Increasing Network Size and Training Throughput of FPGA Restricted Boltzmann Machines Using Dropout. | Jiang Su, David B. Thomas, Peter Y. K. Cheung |
| 2016 | FPGA | Knowledge is Power: Module-level Sensing for Runtime Optimisation (Abstact Only). | James J. Davis, Eddie Hung, Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung, George A. Constantinides |
| 2015 | FPL | Preface. | Peter Y. K. Cheung, Wayne Luk, Cristina Silvano |
| 2014 | DATE | Image progressive acquisition for hardware systems. | Jianxiong Liu, Christos-Savvas Bouganis, Peter Y. K. Cheung |
| 2014 | FCCM | SMCGen: Generating Reconfigurable Design for Sequential Monte Carlo Applications. | Thomas C. P. Chau, Maciej Kurek, James Stanley Targett, Jake Humphrey, Georgios Skouroupathis, Alison Eele, Jan M. Maciejowski, Benjamin Cope, Kathryn Cobden, Philip Heng Wai Leong, Peter Y. K. Cheung, Wayne Luk |
| 2014 | FCCM | Reducing Overheads for Fault-Tolerant Datapaths with Dynamic Partial Reconfiguration. | James J. Davis, Peter Y. K. Cheung |
| 2014 | FCCM | Timing Fault Detection in FPGA-Based Circuits. | Edward A. Stott, Joshua M. Levine, Peter Y. K. Cheung, Nachiket Kapre |
| 2014 | FPGA | Dynamic voltage & frequency scaling with online slack measurement. | Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung |
| 2014 | FPL | Achieving low-overhead fault tolerance for parallel accelerators with dynamic partial reconfiguration. | James J. Davis, Peter Y. K. Cheung |
| 2013 | FPL | A variation-adaptive retiming method exploiting reconfigurability. | Zhenyu Guan, Justin S. J. Wong, Sumanta Chaudhuri, George A. Constantinides, Peter Y. K. Cheung |
| 2013 | FPL | SMI: Slack Measurement Insertion for online timing monitoring in FPGAs. | Joshua M. Levine, Edward A. Stott, George A. Constantinides, Peter Y. K. Cheung |
| 2012 | FCCM | Online Measurement of Timing in Circuits: For Health Monitoring and Dynamic Voltage & Frequency Scaling. | Joshua M. Levine, Edward A. Stott, George A. Constantinides, Peter Y. K. Cheung |
| 2012 | FPL | Adaptive Sequential Monte Carlo approach for real-time applications. | Thomas C. P. Chau, Wayne Luk, Peter Y. K. Cheung, Alison Eele, Jan M. Maciejowski |
| 2012 | FPL | A two-stage variation-aware placement method for FPGAS exploiting variation maps classification. | Zhenyu Guan, Justin S. J. Wong, Sumanta Chaudhuri, George A. Constantinides, Peter Y. K. Cheung |
| 2012 | FPL | Early performance estimation of image compression methods on soft processors. | Adam Powell, Christos-Savvas Bouganis, Peter Y. K. Cheung |
| 2011 | FPGA | Health monitoring of live circuits in FPGAs based on time delay measurement (abstract only). | Joshua M. Levine, Edward A. Stott, George A. Constantinides, Peter Y. K. Cheung |
| 2011 | FPGA | Improved delay measurement method in FPGA based on transition probability. | Justin S. J. Wong, Peter Y. K. Cheung |
| 2011 | FPL | Improving FPGA Reliability with Wear-Levelling. | Edward A. Stott, Peter Y. K. Cheung |
| 2010 | DATE | Exploration of hardware sharing for image encoders. | Sebastin Lpez, Roberto Sarmiento, Philip G. Potter, Wayne Luk, Peter Y. K. Cheung |
| 2010 | FCCM | Energy-Aware Optimisation for Run-Time Reconfiguration. | Tobias Becker, Wayne Luk, Peter Y. K. Cheung |
| 2010 | FPGA | Degradation in FPGAs: measurement and modelling. | Edward A. Stott, Justin S. J. Wong, N. Pete Sedcole, Peter Y. K. Cheung |
| 2010 | FPL | GPU Versus FPGA for High Productivity Computing. | David Huw Jones, Adam Powell, Christos-Savvas Bouganis, Peter Y. K. Cheung |
| 2010 | FPL | Degradation Analysis and Mitigation in FPGAs. | Edward A. Stott, Justin S. J. Wong, Peter Y. K. Cheung |
| 2010 | ICONIP | A Salient Region Detector for GPU Using a Cellular Automata Architecture. | David Huw Jones, Adam Powell, Christos-Savvas Bouganis, Peter Y. K. Cheung |
| 2009 | DATE | Partition-based exploration for reconfigurable JPEG designs. | Philip G. Potter, Wayne Luk, Peter Y. K. Cheung |
| 2009 | FCCM | Benchmarking Reconfigurable Architectures in the Mobile Domain. | Peter Jamieson, Tobias Becker, Wayne Luk, Peter Y. K. Cheung, Tero Rissa, Teemu Pitknen |
| 2009 | FPL | Compensating for variability in FPGAs by re-mapping and re-placement. | N. Pete Sedcole, Edward A. Stott, Peter Y. K. Cheung |
| 2009 | FPL | Area estimation and optimisation of FPGA routing fabrics. | Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung |
| 2009 | ICIP | A sensor-based approach to linear blur identification for real-time video enhancement. | Maria E. Angelopoulou, Christos-Savvas Bouganis, Peter Y. K. Cheung |
| 2009 | ISCAS | Throughput Maximization for Wave-pipelined Interconnects using Cascaded Buffers and Transistor Sizing. | Li Wang, Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung |
| 2008 | DATE | Using Reconfigurable Logic to Optimise GPU Memory Accesses. | Ben Cope, Peter Y. K. Cheung, Wayne Luk |
| 2008 | FPGA | High-throughput interconnect wave-pipelining for global communication in FPGAs. | Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk |
| 2008 | FPGA | Measuring and modeling FPGA clock variability. | N. Pete Sedcole, Justin S. J. Wong, Peter Y. K. Cheung |
| 2008 | FPL | Towards benchmarking energy efficiency of reconfigurable architectures. | Tobias Becker, Peter Jamieson, Wayne Luk, Peter Y. K. Cheung, Tero Rissa |
| 2008 | FPL | Combining data reuse exploitationwith data-level parallelization for FPGA targeted hardware compilation: A geometric programming framework. | Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung |
| 2008 | FPL | Fault tolerant methods for reliability in FPGAs. | Edward A. Stott, N. Pete Sedcole, Peter Y. K. Cheung |
| 2008 | FPL | Combating process variation on FPGAS with a precise at-speed delay measurement method. | Justin S. J. Wong, Peter Y. K. Cheung, N. Pete Sedcole |
| 2008 | ICIP | Video enhancement on an adaptive image sensor. | Maria E. Angelopoulou, Christos-Savvas Bouganis, Peter Y. K. Cheung |
| 2008 | ISCAS | Glitch-aware output switching activity from word-level statistics. | Jonathan A. Clarke, George A. Constantinides, Peter Y. K. Cheung, Alastair M. Smith |
| 2007 | FCCM | A Hybrid Memory Sub-system for Video Coding Applications. | Su-Shin Ang, George A. Constantinides, Wayne Luk, Peter Y. K. Cheung |
| 2007 | FCCM | Enhancing Relocatability of Partial Bitstreams for Run-Time Reconfiguration. | Tobias Becker, Wayne Luk, Peter Y. K. Cheung |
| 2007 | FCCM | Efficient Mapping of Dimensionality Reduction Designs onto Heterogeneous FPGAs. | Christos-Savvas Bouganis, Iosifina Pournara, Peter Y. K. Cheung |
| 2007 | FCCM | Automatic On-chip Memory Minimization for Data Reuse. | Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung |
| 2007 | FPGA | Parametric yield in FPGAs due to within-die delay variations: a quantitative analysis. | N. Pete Sedcole, Peter Y. K. Cheung |
| 2007 | FPL | On the feasibility of early routing capacitance estimation for FPGAs. | Jonathan A. Clarke, George A. Constantinides, Peter Y. K. Cheung |
| 2007 | FPL | Efficient mapping of a Kalman filter into an FPGA using Taylor Expansion. | Yang Liu, Christos-Savvas Bouganis, Peter Y. K. Cheung |
| 2007 | ICIP | A Novel Video Parsing Algorithm Utilizing the Pleasure-Arousal-Dominance Emotional Information. | Sutjipto Arifin, Peter Y. K. Cheung |
| 2006 | DATE | A novel FPGA-based implementation of time adaptive clustering for logical story unit segmentation. | Sutjipto Arifin, Peter Y. K. Cheung |
| 2006 | DATE | Hardware efficient architectures for Eigenvalue computation. | Yang Liu, Christos-Savvas Bouganis, Peter Y. K. Cheung, Philip Heng Wai Leong, Stephen J. Motley |
| 2006 | FCCM | A Novel Hueristic and Provable Bounds for Reconfigurable Architecture Design. | Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung |
| 2006 | FPGA | Yield enhancements of design-specific FPGAs. | Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko |
| 2006 | FPL | Towards Affective Level Video Applications: A Novel FPGA-Based Video Arousal Content Modeling System. | Sutjipto Arifin, Peter Y. K. Cheung |
| 2006 | FPL | FPGA-Accelerated Pre-Attentive Segmentation in Primary Visual Cortex. | Christos-Savvas Bouganis, Peter Y. K. Cheung, Zhaoping Li |
| 2006 | FPL | Reconfiguration and Fine-Grained Redundancy for Fault Tolerance in FPGAs. | Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko |
| 2006 | FPL | Efficient Realtime FPGA Implementation of the Trace Transform. | Suhaib A. Fahmy, Christos-Savvas Bouganis, Peter Y. K. Cheung, Wayne Luk |
| 2006 | FPL | On-FPGA Communication Architectures and Design Factors. | Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk |
| 2006 | FPL | A Novel Heuristic and Provable Bounds for Reconfigurable Architecture Design. | Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung |
| 2006 | ICIP | User Attention Based Arousal Content Modeling. | Sutjipto Arifin, Peter Y. K. Cheung |
| 2006 | ICIP | A Spatiotemporal Saliency Framework. | Yang Liu, Christos-Savvas Bouganis, Peter Y. K. Cheung |
| 2006 | ISCAS | Fast word-level power models for synthesis of FPGA-based arithmetic. | Jonathan A. Clarke, Altaf Abdul Gaffar, George A. Constantinides, Peter Y. K. Cheung |
| 2005 | CASES | Automating custom-precision function evaluation for embedded processors. | Ray C. C. Cheung, Dong-U Lee, Oskar Mencer, Wayne Luk, Peter Y. K. Cheung |
| 2005 | DATE | Reconfigurable Elliptic Curve Cryptosystems on a Chip. | Ray C. C. Cheung, Wayne Luk, Peter Y. K. Cheung |
| 2005 | DATE | Hardware Acceleration of Hidden Markov Model Decoding for Person Detection. | Suhaib A. Fahmy, Peter Y. K. Cheung, Wayne Luk |
| 2005 | FCCM | A Novel 2D Filter Design Methodology for Heterogeneous Devices. | Christos-Savvas Bouganis, George A. Constantinides, Peter Y. K. Cheung |
| 2005 | FPGA | Analysis of yield loss due to random photolithographic defects in the interconnect structure of FPGAs. | Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko |
| 2005 | FPGA | Exploration of heterogeneous reconfigurable architectures (abstract only). | Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung |
| 2005 | FPL | Heterogeneity Exploration for Multiple 2D Filter Designs. | Christos-Savvas Bouganis, Peter Y. K. Cheung, George A. Constantinides |
| 2005 | FPL | Yield modelling and Yield Enhancement for FPGAs using Fault Tolerance Schemes. | Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko |
| 2005 | FPL | Error Modelling of Dual FiXed-point Arithmetic and its Application in Field Programmable Logic. | Chun Te Ewe, Peter Y. K. Cheung, George A. Constantinides |
| 2005 | FPL | Novel FPGA-Based Implementation of Median and Weighted Median Filters for Image Processing. | Suhaib A. Fahmy, Peter Y. K. Cheung, Wayne Luk |
| 2005 | FPL | Using DSP Blocks For ROM Replacement: A Novel Synthesis Flow. | Gareth W. Morris, George A. Constantinides, Peter Y. K. Cheung |
| 2005 | FPL | Power and Area Optimization for Multiple Restricted Multiplication. | Nalin Sidahao, George A. Constantinides, Peter Y. K. Cheung |
| 2005 | FPL | An Analytical Approach to Generation and Exploration of Reconfigurable Architectures. | Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung |
| 2005 | ISCAS | A novel 2D filter design methodology. | Christos-Savvas Bouganis, George A. Constantinides, Peter Y. K. Cheung |
| 2005 | ISCAS | A heuristic approach for multiple restricted multiplication. | Nalin Sidahao, George A. Constantinides, Peter Y. K. Cheung |
| 2004 | DATE | A Novel Implementation of Tile-Based Address Mapping. | Sambuddhi Hettiaratchi, Peter Y. K. Cheung |
| 2004 | FCCM | Unifying Bit-Width Optimisation for Fixed-Point and Floating-Point Designs. | Altaf Abdul Gaffar, Oskar Mencer, Wayne Luk, Peter Y. K. Cheung |
| 2004 | FCCM | Migrating Functionality from ROMS to Embedded Multipliers. | Gareth W. Morris, George A. Constantinides, Peter Y. K. Cheung |
| 2004 | FCCM | A Structured System Methodology for FPGA Based System-on-A-Chip Design. | N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk |
| 2004 | FPL | A Steerable Complex Wavelet Construction and Its Implementation on FPGA. | Christos-Savvas Bouganis, Peter Y. K. Cheung, Jeffrey Ng, Anil A. Bharath |
| 2004 | FPL | BIST Based Interconnect Fault Location for FPGAs. | Nicola Campregher, Peter Y. K. Cheung, Milan Vasilko |
| 2004 | FPL | Dual Fixed-Point: An Efficient Alternative to Floating-Point Computation. | Chun Te Ewe, Peter Y. K. Cheung, George A. Constantinides |
| 2004 | FPL | SoftSONIC: A Customisable Modular Platform for Video Applications. | Tero Rissa, Peter Y. K. Cheung, Wayne Luk |
| 2004 | FPL | A Structured Methodology for System-on-an-FPGA Design. | N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk |
| 2004 | FPL | Multiple Restricted Multiplication. | Nalin Sidahao, George A. Constantinides, Peter Y. K. Cheung |
| 2004 | ISCAS | Autonomous Memory Block for reconfigurable computing. | Wim J. C. Melis, Peter Y. K. Cheung, Wayne Luk |
| 2003 | DATE | Mesh Partitioning Approach to Energy Efficient Data Layout. | Sambuddhi Hettiaratchi, Peter Y. K. Cheung |
| 2003 | FCCM | A Hardware Gaussian Noise Generator for Channel Code Evaluation. | Dong-U Lee, Wayne Luk, John D. Villasenor, Peter Y. K. Cheung |
| 2003 | FPL | Non-uniform Segmentation for Hardware Function Evaluation. | Dong-U Lee, Wayne Luk, John D. Villasenor, Peter Y. K. Cheung |
| 2003 | FPL | Globally Asynchronous Locally Synchronous FPGA Architectures. | Andrew Royal, Peter Y. K. Cheung |
| 2003 | FPL | A Reconfigurable Platform for Real-Time Embedded Video Image Processing. | N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk |
| 2003 | FPL | A Unified Codesign Run-Time Environment for the UltraSONIC Reconfigurable Computer. | Theerayod Wiangtong, Peter Y. K. Cheung, Wayne Luk |
| 2003 | FPL | Cluster-Driven Hardware/Software Partitioning and Scheduling Approach for a Reconfigurable Computer System. | Theerayod Wiangtong, Peter Y. K. Cheung, Wayne Luk |
| 2003 | ISCAS | Architectures for function evaluation on FPGAs. | Nalin Sidahao, George A. Constantinides, Peter Y. K. Cheung |
| 2003 | ISCAS | Multitasking in hardware-software codesign for reconfigurable computer. | Theerayod Wiangtong, Peter Y. K. Cheung, Wayne Luk |
| 2003 | ISCAS | SONICmole: a debugging environment for the UltraSONIC reconfigurable computer. | Theerayod Wiangtong, Chun Te Ewe, Peter Y. K. Cheung |
| 2002 | DATE | Performance-Area Trade-Off of Address Generators for Address Decoder-Decoupled Memory. | Sambuddhi Hettiaratchi, Peter Y. K. Cheung, Thomas J. W. Clarke |
| 2002 | FCCM | Optimum Wordlength Allocation. | George A. Constantinides, Peter Y. K. Cheung, Wayne Luk |
| 2002 | FCCM | Customising Floating-Point Designs. | Altaf Abdul Gaffar, Wayne Luk, Peter Y. K. Cheung, Nabeel Shirazi |
| 2002 | FCCM | Reconfigurable Shape-Adaptive Template Matching Architectures. | Jrn Gause, Peter Y. K. Cheung, Wayne Luk |
| 2002 | FCCM | Image Registration of Real-Time Video Data Using the SONIC Reconfigurable Computer Platform. | Wim J. C. Melis, Peter Y. K. Cheung, Wayne Luk |
| 2002 | FCCM | Tabu Search with Intensification Strategy for Functional Partitioning in Hardware-Software Codesign. | Theerayod Wiangtong, Peter Y. K. Cheung, Wayne Luk |
| 2002 | FPL | Automating Customisation of Floating-Point Designs. | Altaf Abdul Gaffar, Wayne Luk, Peter Y. K. Cheung, Nabeel Shirazi, James Hwang |
| 2002 | FPL | Image Registration of Real-Time Broadcast Video Using the UltraSONIC Reconfigurable Computer. | Wim J. C. Melis, Peter Y. K. Cheung, Wayne Luk |
| 2002 | FPL | Run-Time Adaptive Flexible Instruction Processors. | Shay Ping Seng, Wayne Luk, Peter Y. K. Cheung |
| 2002 | ICCAD | Energy efficient address assignment through minimized memory row switching. | Sambuddhi Hettiaratchi, Peter Y. K. Cheung, Thomas J. W. Clarke |
| 2001 | DATE | Heuristic datapath allocation for multiple wordlength systems. | George A. Constantinides, Peter Y. K. Cheung, Wayne Luk |
| 2001 | FCCM | The Multiple Wordlength Paradigm. | George A. Constantinides, Peter Y. K. Cheung, Wayne Luk |
| 2001 | FCCM | The Effect of FPGA Granularity on Video Codec Implementations. | Jrn Gause, Carsten Reuter, Holger Kropp, Peter Y. K. Cheung, Wayne Luk |
| 2001 | FPL | A Digit-Serial Structure for Reconfigurable Multipliers. | Chakkapas Visavakul, Peter Y. K. Cheung, Wayne Luk |
| 2001 | ISCAS | MASH delta-sigma modulators for wideband and multi-standard applications. | Kei-Tee Tiew, Alison J. Payne, Peter Y. K. Cheung |
| 2000 | CASES | Flexible instruction processors. | Shay Ping Seng, Wayne Luk, Peter Y. K. Cheung |
| 2000 | FCCM | Multiple Precision for Resource Minimization. | George A. Constantinides, Peter Y. K. Cheung, Wayne Luk |
| 2000 | FPL | Multiple-Wordlength Resource Binding. | George A. Constantinides, Peter Y. K. Cheung, Wayne Luk |
| 2000 | FPL | Static and Dynamic Reconfigurable Designs for a 2D Shape-Adaptive DCT. | Jrn Gause, Peter Y. K. Cheung, Wayne Luk |
| 2000 | ISCAS | Roundoff-noise shaping in filter design. | George A. Constantinides, Peter Y. K. Cheung, Wayne Luk |
| 1999 | FCCM | SONIC - A Plug-In Architecture for Video Processing. | Simon D. Haynes, Peter Y. K. Cheung, Wayne Luk, John Stone |
| 1999 | FCCM | Reconfigurable Computing for Augmented Reality. | Wayne Luk, T. K. Lee, J. Rice, Nabeel Shirazi, Peter Y. K. Cheung |
| 1999 | FPL | Untitled record | George A. Constantinides, Peter Y. K. Cheung, Wayne Luk |
| 1999 | FPL | SONIC - A Plug-In Architecture for Video Processing. | Simon D. Haynes, Peter Y. K. Cheung, Wayne Luk, John Stone |
| 1999 | FPL | Quantitative Analysis of Run-Time Reconfigurable Database Search. | Nabeel Shirazi, Wayne Luk, Dan Benyamin, Peter Y. K. Cheung |
| 1998 | FCCM | A Reconfigurable Multiplier Array For Video Image Processing Tasks, Suitable For Embedding In An FPGA Structure. | Simon D. Haynes, Peter Y. K. Cheung |
| 1998 | FCCM | Automating Production of Run-Time Reconfigurable Designs. | Nabeel Shirazi, Wayne Luk, Peter Y. K. Cheung |
| 1998 | FPL | Run-Time Management of Dynamically Recongigurable Designs. | Nabeel Shirazi, Wayne Luk, Peter Y. K. Cheung |
| 1997 | DATE | Improved diagnosis of realistic interconnect shorts. | Jos T. de Sousa, Peter Y. K. Cheung |
| 1997 | FCCM | Compilation tools for run-time reconfigurable designs. | Wayne Luk, Nabeel Shirazi, Peter Y. K. Cheung |
| 1997 | FPL | A reconfigurable data-localised array for morphological algorithms. | Anjit Sekhar Chaudhuri, Peter Y. K. Cheung, Wayne Luk |
| 1997 | FPL | Pipeline morphing and virtual pipelines. | Wayne Luk, Nabeel Shirazi, Shaori Guo, Peter Y. K. Cheung |
| 1997 | FPL | Riley-2: A flexible platform for codesign and dynamic reconfigurable computing research. | Patrick I. Mackinlay, Peter Y. K. Cheung, Wayne Luk, Richard Sandiford |
| 1997 | ICCD | Asnchronous Wrapper for Heterogeneous Systems. | David S. Bormann, Peter Y. K. Cheung |
| 1996 | DATE | Realistic Fault Extraction for Boards. | Jos T. de Sousa, T. Shen, Peter Y. K. Cheung |
| 1996 | FCCM | On the viability of FPGA-based integrated coprocessors. | Osama T. Albaharna, Peter Y. K. Cheung, Thomas J. Clarke |
| 1996 | FCCM | Modelling and optimising run-time reconfigurable systems. | Wayne Luk, Nabeel Shirazi, Peter Y. K. Cheung |
| 1994 | ICCD | Area & Time Limitations of FPGA-based Virtual Hardware. | Osama T. Albaharna, Peter Y. K. Cheung, Thomas J. Clarke |
| 1994 | ISCAS | Analog Fault Diagnosis - A Practical Approach. | Salman Ahmed, Peter Y. K. Cheung |
| 1994 | ISCAS | Virtual Hardware and the Limits of Computational Speed-up. | Osama T. Albaharna, Peter Y. K. Cheung, Thomas J. Clarke |
| 1994 | ISCAS | A Method of Representative Fault Selection in Digital Circuits for ATPG. | Akachai Sang-In, Peter Y. K. Cheung |
| 1993 | ISCAS | A New Schematic-driven Floorplanning Algorithm for Analog Cell Layout. | Nasir-ud-Din Gohar, Peter Y. K. Cheung |
| 1991 | ICCD | A Tag Coprocessor Architecture for Symbolic Languages. | Vicente Fuentes-Snchez, Peter Y. K. Cheung |