| 2024 | VLSID | ROBUST: RTL OBfuscation USing Bi-functional Polymorphic OperaTors. | Haimanti Chakraborty, Ranga Vemuri |
| 2024 | VLSID | Pattern Based Synthetic Benchmark Generation for Hardware Security Applications. | Juneet Kumar Meka, Satya AmarKant Marupureddy, Ranga Vemuri |
| 2024 | VLSID | Enhancing Output Corruption Through GSHE Switch Based Logic Encryption. | Nikhil Saxena, Ranga Vemuri |
| 2024 | VLSID | Trojan Localization Using Information Flow Tracking Properties in SoC Designs. | Suriya Srinivasan, Ranga Vemuri |
| 2023 | VLSID | ASPIRE: An Intermediate Representation for Abstract Security Policies. | Padmaja Bhamidipati, Ranga Vemuri |
| 2023 | VLSID | Mutation Analysis and Model Checking Guided Test Generation for SoC Run-Time Monitors. | Suriya Srinivasan, Ranga Vemuri |
| 2023 | VLSID | Word-Level Structure Identification In FPGA Designs Using Cell Proximity Information. | Aparajithan Nathamuni Venkatesan, Ram Venkat Narayanan, Kishore Pula, Sundarakumar Muthukumaran, Ranga Vemuri |
| 2022 | ICCD | Model Checking Leveraged Error Localization for Complex RTL Designs. | Suriya Srinivasan, Ranga Vemuri |
| 2021 | ICCD | Efficient Methods for SoC Trust Validation Using Information Flow Verification. | Khitam M. Alatoun, Shanmukha Murali Achyutha, Ranga Vemuri |
| 2020 | VLSID | StateLock: State Transition Based Logic Locking for Sequential Circuits. | Yasaswy Kasarabada, Ranga Vemuri |
| 2019 | VLSID | A State Encoding Methodology for Side-Channel Security vs. Power Trade-off Exploration. | Richa Agrawal, Mike Borowczak, Ranga Vemuri |
| 2018 | ICCD | Reverse Engineering of Split Manufactured Sequential Circuits Using Satisfiability Checking. | Suyuan Chen, Ranga Vemuri |
| 2018 | VLSID | Combined Inference and Satisfiability Based Methods for Complete Signal Restoration in Post-Silicon Validation. | Xiaobang Liu, Ranga Vemuri |
| 2017 | ICCD | Effective Signal Restoration in Post-Silicon Validation. | Xiaobang Liu, Ranga Vemuri |
| 2016 | ICCD | A novel simulation based approach for trace signal selection in silicon debug. | Prabanjan Komari, Ranga Vemuri |
| 2010 | ICCAD | Stretching the limit of microarchitectural level leakage control with Adaptive Light-Weight Vth Hopping. | Hao Xu, Wen-Ben Jone, Ranga Vemuri |
| 2010 | ICCAD | Current shaping and multi-thread activation for fast and reliable power mode transition in multicore designs. | Hao Xu, Ranga Vemuri, Wen-Ben Jone |
| 2010 | VLSID | Novel Vth Hopping Techniques for Aggressive Runtime Leakage Control. | Hao Xu, Wen-Ben Jone, Ranga Vemuri |
| 2009 | DATE | A graph grammar based approach to automated multi-objective analog circuit design. | Angan Das, Ranga Vemuri |
| 2009 | DATE | Selective light Vth hopping (SLITH): Bridging the gap between runtime dynamic and leakage. | Hao Xu, Ranga Vemuri, Wen-Ben Jone |
| 2009 | ICCAD | Temporal and spatial idleness exploitation for optimal-grained leakage control. | Hao Xu, Ranga Vemuri, Wen-Ben Jone |
| 2009 | ICCD | Accurate estimation of vector dependent leakage power in the presence of process variations. | Romana Fernandes, Ranga Vemuri |
| 2009 | VLSID | Variation-Aware Macromodeling and Synthesis of Analog Circuits Using Spline Center and Range Method and Dynamically Reduced Design Space. | Shubhankar Basu, Balaji Kommineni, Ranga Vemuri |
| 2009 | VLSID | Fuzzy Logic Based Guidance to Graph Grammar Framework for Automated Analog Circuit Design. | Angan Das, Ranga Vemuri |
| 2009 | VLSID | Efficient Synthesis of a Uniformly Spread Layout Aware Pareto Surface for Analog Circuits. | Almitra Pradhan, Ranga Vemuri |
| 2008 | DAC | Topology synthesis of analog circuits based on adaptively generated building blocks. | Angan Das, Ranga Vemuri |
| 2008 | DATE | Fast Analog Circuit Synthesis Using Sensitivity Based Near Neighbor Searches. | Almitra Pradhan, Ranga Vemuri |
| 2008 | ICCAD | Accurate energy breakeven time estimation for run-time power gating. | Hao Xu, Wen-Ben Jone, Ranga Vemuri |
| 2008 | ICCD | Run-time Active Leakage Reduction by power gating and reverse body biasing: An eNERGY vIEW. | Hao Xu, Ranga Vemuri, Wen-Ben Jone |
| 2008 | ISCAS | ATLAS: An adaptively formed hierarchical cell library based analog synthesis framework. | Angan Das, Ranga Vemuri |
| 2008 | ISLPED | Dynamic virtual ground voltage estimation for power gating. | Hao Xu, Ranga Vemuri, Wen-Ben Jone |
| 2008 | VLSID | Mismatch Aware Analog Performance Macromodeling Using Spline Center and Range Regression on Adaptive Samples. | Shubhankar Basu, Balaji Kommineni, Ranga Vemuri |
| 2008 | VLSID | On the Use of Hash Tables for Efficient Analog Circuit Synthesis. | Almitra Pradhan, Ranga Vemuri |
| 2008 | VLSID | Reduced Complementary Dynamic and Differential Logic: A CMOS Logic Style for DPA-Resistant Secure IC Design. | Srividhya Rammohan, Vijay Sundaresan, Ranga Vemuri |
| 2007 | ICCD | Power variations of multi-port routers in an application-specific NoC design : A case study. | Balasubramanian Sethuraman, Ranga Vemuri |
| 2007 | ICMLA | A spline based regression technique on interval valued noisy data. | Balaji Kommineni, Shubhankar Basu, Ranga Vemuri |
| 2007 | ISCAS | GAPSYS: A GA-based Tool for Automated Passive Analog Circuit Synthesis. | Angan Das, Ranga Vemuri |
| 2007 | ISLPED | Multicasting based topology generation and core mapping for a power efficient networks-on-chip. | Balasubramanian Sethuraman, Ranga Vemuri |
| 2007 | VLSID | A Force-directed Approach for Fast Generation of Efficient Multi-Port NoC Architectures. | Balasubramanian Sethuraman, Ranga Vemuri |
| 2007 | VLSID | Efficient Symbolic Sensitivity based Parasitic-Inclusive Optimization in Layout Aware Analog Circuit Synthesis. | Huiying Yang, Ranga Vemuri |
| 2006 | DATE | optiMap: a tool for automated generation of noc architectures using multi-port routers for FPGAs. | Balasubramanian Sethuraman, Ranga Vemuri |
| 2006 | DATE | Efficient temperature-dependent symbolic sensitivity analysis and symbolic performance evaluation in analog circuit synthesis. | Huiying Yang, Ranga Vemuri |
| 2006 | FPL | Multi2 Router: A Novel Multi Local Port Router Architecture with Broadcast Facility for FPGA-Based Networks-on-Chip. | Balasubramanian Sethuraman, Ranga Vemuri |
| 2006 | ICCAD | Studying a GALS FPGA architecture using a parameterized automatic design flow. | Xin Jia, Ranga Vemuri |
| 2006 | ISCAS | Exact hierarchical symbolic analysis of large analog networks using a general interconnection template. | Mukesh Ranjan, Ranga Vemuri |
| 2006 | VLSID | Parasitic Aware Routing Methodology Based on Higher Order RLCK Moment Metrics. | Amitava Bhaduri, Ranga Vemuri |
| 2006 | VLSID | Symbolic Time-Domain Behavioral and Performance Modeling of Linear Analog Circuits Using an Efficient Symbolic Newton-Iteration Algorithm for Pole Extraction. | Ritochit Chakraborty, Mukesh Ranjan, Ranga Vemuri |
| 2006 | VLSID | Efficient Analog Performance Macromodeling via Sequential Design Space Decomposition. | Mengmeng Ding, Ranga Vemuri |
| 2006 | VLSID | CAD Tools for a Globally Asynchronous Locally Synchronous FPGA Architecture. | Xin Jia, Ranga Vemuri |
| 2005 | ASPDAC | An error-driven adaptive grid refinement algorithm for automatic generation of analog circuit performance macromodels. | Mengmeng Ding, Glenn Wolfe, Ranga Vemuri |
| 2005 | ASPDAC | Using GALS architecture to reduce the impact of long wire delay on FPGA performance. | Xin Jia, Ranga Vemuri |
| 2005 | ASPDAC | Efficient symbolic sensitivity analysis of analog circuits using element-coefficient diagrams. | Huiying Yang, Mukesh Ranjan, Wim Verhaegen, Mengmeng Ding, Ranga Vemuri, Georges G. E. Gielen |
| 2005 | DAC | A combined feasibility and performance macromodel for analog circuits. | Mengmeng Ding, Ranga Vemuri |
| 2005 | DATE | Multi-Placement Structures for Fast and Optimized Placement in Analog Circuit Synthesis. | Raoul F. Badaoui, Ranga Vemuri |
| 2005 | DATE | Inductive and Capacitive Coupling Aware Routing Methodology Driven by a Higher Order RLCK Moment Metric. | Amitava Bhaduri, Ranga Vemuri |
| 2005 | DATE | A Two-Level Modeling Approach to Analog Circuit Performance Macromodeling. | Mengmeng Ding, Ranga Vemuri |
| 2005 | DATE | An Iterative Algorithm for Battery-Aware Task Scheduling on Portable Computing Platforms. | Jawad Khan, Ranga Vemuri |
| 2005 | FCCM | The GAPLA: A Globally Asynchronous Locally Synchronous FPGA Architecture. | Xin Jia, Ranga Vemuri |
| 2005 | FPL | PAHLS: Towards Run-Time Synthesis for FPGAs. | Renqiu Huang, Ranga Vemuri |
| 2005 | FPL | A Novel Asynchronous FPGA Architecture Design and Its Performance Evaluation. | Xin Jia, Ranga Vemuri |
| 2005 | FPL | Energy Management in Battery-Powered Sensor Networks with Reconfigurable Computing Nodes. | Jawad Khan, Ranga Vemuri |
| 2005 | ICCAD | Hierarchical performance macromodels of feasible regions for synthesis of analog and RF circuits. | Anuradha Agarwal, Ranga Vemuri |
| 2005 | ICCD | Layout-Aware RF Circuit Synthesis Driven by Worst Case Parasitic Corners. | Anuradha Agarwal, Ranga Vemuri |
| 2005 | ISCAS | Analog VLSI circuit-level synthesis using multi-placement structures. | Raoul F. Badaoui, Ranga Vemuri |
| 2005 | VLSID | An Active Learning Scheme Using Support Vector Machines for Analog Circuit Feasibility Classification. | Mengmeng Ding, Ranga Vemuri |
| 2005 | VLSID | On-Line Synthesis for Partially Reconfigurable FPGAs. | Renqiu Huang, Ranga Vemuri |
| 2005 | VLSID | On Physical-Aware Synthesis of Vertically Integrated 3D Systems. | Madhubanti Mukherjee, Ranga Vemuri |
| 2004 | DAC | Fast and accurate parasitic capacitance models for layout-aware. | Anuradha Agarwal, Hemanth Sampath, Veena Yelamanchili, Ranga Vemuri |
| 2004 | DAC | An efficient algorithm for finding empty space for online FPGA placement. | Manish Handa, Ranga Vemuri |
| 2004 | DATE | Accurate Estimation of Parasitic Capacitances in Analog Circuits. | Anuradha Agarwal, Hemanth Sampath, Veena Yelamanchili, Ranga Vemuri |
| 2004 | DATE | A Fast Algorithm for Finding Maximal Empty Rectangles for Dynamic FPGA Placement. | Manish Handa, Ranga Vemuri |
| 2004 | DATE | Fast, Layout-Inclusive Analog Circuit Synthesis using Pre-Compiled Parasitic-Aware Symbolic Performance Models. | Mukesh Ranjan, Wim Verhaegen, Anuradha Agarwal, Hemanth Sampath, Ranga Vemuri, Georges G. E. Gielen |
| 2004 | FPL | An Integrated Online Scheduling and Placement Methodology. | Manish Handa, Ranga Vemuri |
| 2004 | FPL | Analysis of a Hybrid Interconnect Architecture for Dynamically Reconfigurable FPGAs. | Renqiu Huang, Manish Handa, Ranga Vemuri |
| 2004 | FPL | A Dynamically Reconfigurable Asynchronous FPGA Architecture. | Xin Jia, Jayanthi Rajagopalan, Ranga Vemuri |
| 2004 | FPL | An Efficient Battery-Aware Task Scheduling Methodology for Portable RC Platforms. | Jawad Khan, Ranga Vemuri |
| 2004 | ICCAD | Analysis and evaluation of a hybrid interconnect structure for FPGAs. | Renqiu Huang, Ranga Vemuri |
| 2004 | ICCAD | Adaptive sampling and modeling of analog circuit performance parameters with pseudo-cubic splines. | Ranga Vemuri, Glenn Wolfe |
| 2004 | ICCD | Simultaneous Scheduling, Binding and Layer Assignment for Synthesis of Vertically Integrated 3D Systems. | Madhubanti Mukherjee, Ranga Vemuri |
| 2003 | ICCD | A Novel Synthesis Strategy Driven by Partial Evaluation Based Circuit Reduction for Application Specific DSP Circuits. | Madhubanti Mukherjee, Ranga Vemuri |
| 2003 | VLSID | A Fast Macro Based Compilation Methodology for Partially Reconfigurable FPGA Designs. | Manish Handa, Rajesh Radhakrishnan, Madhubanti Mukherjee, Ranga Vemuri |
| 2002 | DATE | A Functional Specification Notation for Co-Design of Mixed Analog-Digital Systems. | Alex Doboli, Ranga Vemuri |
| 2002 | FPL | iPACE-V1: A Portable Adaptive Computing Engine for Real Time Applications. | Jawad Khan, Manish Handa, Ranga Vemuri |
| 2002 | VLSID | Framework for Synthesis of Virtual Pipelines. | Srinivasan Dasasathyan, Rajesh Radhakrishnan, Ranga Vemuri |
| 2001 | DAC | Integrated High-Level Synthesis and Power-Net Routing for Digital Design under Switching Noise Constraints. | Alex Doboli, Ranga Vemuri |
| 2001 | DAC | Behavioral Partitioning in the Synthesis of Mixed Analog-Digital Systems. | Sree Ganesan, Ranga Vemuri |
| 2001 | DATE | A regularity-based hierarchical symbolic analysis method for large-scale analog networks. | Alex Doboli, Ranga Vemuri |
| 2001 | DATE | Hierarchical memory mapping during synthesis in FPGA-based reconfigurable computers. | Iyad Ouaiss, Ranga Vemuri |
| 2001 | DATE | On the verification of synthesized designs using automatically generated transformational witnesses. | Elena Teica, Rajesh Radhakrishnan, Ranga Vemuri |
| 2001 | FPL | Memory Synthesis for FPGA-Based Reconfigurable Computers. | Amit Kasat, Iyad Ouaiss, Ranga Vemuri |
| 2001 | ISCAS | Hierarchical performance optimization for synthesis of linear analog systems. | Alex Doboli, Ranga Vemuri |
| 2001 | VLSID | Library Binding for High-Level Synthesis of Analog Systems. | Sree Ganesan, Ranga Vemuri |
| 2001 | VLSID | Application Specific Macro Based Synthesis. | Sujatha Sundararaman, Sriram Govindarajan, Ranga Vemuri |
| 2000 | DATE | Technology Mapping and Retargeting for Field-Programmable Analog Arrays. | Sree Ganesan, Ranga Vemuri |
| 2000 | DATE | An Integrated Temporal Partitioning and Partial Reconfiguration Technique for Design Latency Improvement. | Satish Ganesan, Ranga Vemuri |
| 2000 | DATE | Improving the Schedule Quality of Static-List Time-Constrained Scheduling. | Sriram Govindarajan, Ranga Vemuri |
| 2000 | DATE | Efficient Resource Arbitration in Reconfigurable Computing Environments. | Iyad Ouaiss, Ranga Vemuri |
| 2000 | FPL | Tightly Integrated Design Space Exploration with Spatial and Temporal Partitioning in SPARCS. | Sriram Govindarajan, Ranga Vemuri |
| 2000 | ISCAS | A heuristic technique for system-level architecture generation from signal-flow graph representations of analog systems. | Alex Doboli, Nagu R. Dhanwada, Ranga Vemuri |
| 2000 | ISCAS | Scheduling for low power under resource and latency constraints. | Srinivas Katkoori, Ranga Vemuri |
| 2000 | VLSID | Formal Verification of Synthesized Mixed Signal Designs Using *BMDs. | Abhijit Ghosh, Ranga Vemuri |
| 2000 | VLSID | A Technique for Dynamic High-Level Exploration During Behavioral-Partitioning for Multi-Device Architectures. | Sriram Govindarajan, Vinoo Srinivasan, Preetham Lakshmikanthan, Ranga Vemuri |
| 1999 | ASPDAC | Automatic Constraint Transformation with Integrated Parameter Space Exploration in Analog System Synthesis. | Nagu R. Dhanwada, Adrin Nez-Aldana, Ranga Vemuri |
| 1999 | DAC | Behavioral Synthesis of Analog Systems Using Two-layered Design Space Exploration. | Alex Doboli, Adrin Nez-Aldana, Nagu R. Dhanwada, Sree Ganesan, Ranga Vemuri |
| 1999 | DAC | An Automated Temporal Partitioning and Loop Fission Approach for FPGA Based Reconfigurable Synthesis of DSP Applications. | Meenakshi Kaul, Ranga Vemuri, Sriram Govindarajan, Iyad Ouaiss |
| 1999 | DATE | Hierarchical Constraint Transformation Using Directed Interval Search for Analog System Synthesis. | Nagu R. Dhanwada, Adrin Nez-Aldana, Ranga Vemuri |
| 1999 | DATE | A VHDL-AMS Compiler and Architecture Generator for Behavioral Synthesis of Analog Systems. | Alex Doboli, Ranga Vemuri |
| 1999 | DATE | Temporal Partitioning combined with Design Space Exploration for Latency Minimization of Run-Time Reconfigured Designs. | Meenakshi Kaul, Ranga Vemuri |
| 1999 | DATE | Accounting for Various Register Allocation Schemes During Post-Synthesis Verification of RTL Designs. | Nazanin Mansouri, Ranga Vemuri |
| 1999 | DATE | An Analog Performance Estimator for Improving the Effectiveness of CMOS Analog Systems Circuit Synthesis. | Adrin Nez-Aldana, Ranga Vemuri |
| 1999 | FCCM | Task-Level Partitioning and RTL Design Space Exploration for Multi-FPGA Architectures. | Vinoo Srinivasan, Ranga Vemuri |
| 1999 | FPGA | Throughput Optimization with Design Space Exploration During Partitioning for Multi-FPGA Architectures. | Vinoo Srinivasan, Ranga Vemuri |
| 1999 | FPL | Hardware-Software Codesign for Dynamically Reconfigurable Architectures. | Karam S. Chatha, Ranga Vemuri |
| 1999 | ICCD | A Methodology for Rapid Prototyping of Analog Systems. | Sree Ganesan, Ranga Vemuri |
| 1999 | ICCD | Formal Verification of Synthesized Analog Designs. | Abhijit Ghosh, Ranga Vemuri |
| 1999 | ISCAS | A genetic approach to simultaneous parameter space exploration and constraint transformation in analog synthesis. | Nagu R. Dhanwada, Adrin Nez-Aldana, Ranga Vemuri |
| 1999 | VLSID | Component Characterization and Constraint Transformation Based on Directed Intervals for Analog Synthesis. | Nagu R. Dhanwada, Adrin Nez-Aldana, Ranga Vemuri |
| 1999 | VLSID | FAAR: A Router for Field-Programmable Analog Arrays. | Sree Ganesan, Ranga Vemuri |
| 1999 | RSP | An Iterative Algorithm for Partitioning and Scheduling of Area Constrained HW-SW Systems. | Karam S. Chatha, Ranga Vemuri |
| 1998 | DATE | Optimal Temporal Partitioning and Synthesis for Reconfigurable Architectures. | Meenakshi Kaul, Ranga Vemuri |
| 1998 | DATE | Hardware Software Partitioning with Integrated Hardware Design Space Exploration. | Vinoo Srinivasan, Shankar Radhakrishnan, Ranga Vemuri |
| 1998 | FCCM | An Effective Design System for Dynamically Reconfigurable Architectures. | Sriram Govindarajan, Iyad Ouaiss, Meenakshi Kaul, Vinoo Srinivasan, Ranga Vemuri |
| 1998 | FMCAD | A Methodology for Automated Verification of Synthesized RTL Designs and Its Integration with a High-Level Synthesis Tool. | Nazanin Mansouri, Ranga Vemuri |
| 1998 | ICCD | Theorem proving guided development of formal assertions in a resource-constrained scheduler for high-level synthesis. | Naren Narasimhan, Elena Teica, Rajesh Radhakrishnan, Sriram Govindarajan, Ranga Vemuri |
| 1998 | ICCD | Automatic data path abstraction for verification of large scale designs. | Viresh Paruthi, Nazanin Mansouri, Ranga Vemuri |
| 1998 | VLSID | Constraint Allocation in Analog System Synthesis. | Nagu R. Dhanwada, Ranga Vemuri |
| 1998 | VLSID | A Retiming Based Relaxation Heuristic for Resource-Constrained Loop Pipelining. | Vinoo Srinivasan, Ranga Vemuri |
| 1998 | RSP | Performance Evaluation Tool for Rapid Prototyping of Hardware-Software Codesigns. | Karam S. Chatha, Ranga Vemuri |
| 1997 | ASPDAC | A constructive method for data path area estimation during high-level VLSI synthesis. | Natesan Venkateswaran, Anurag Gupta, Srinivas Katkoori, Dinesh Bhatia, Ranga Vemuri |
| 1997 | DAC | Symbolic Evaluation of Performance Models for Tradeoff Visualization. | Jeffrey Walrath, Ranga Vemuri |
| 1997 | DATE | Cone-based clustering heuristic for list-scheduling algorithms. | Sriram Govindarajan, Ranga Vemuri |
| 1997 | DATE | Performance verification using partial evaluation and interval analysis. | Jeffrey Walrath, Ranga Vemuri, W. Bradley |
| 1997 | ICCD | Dynamic Bounding of Successor Force Computations in the Force Directed List Scheduling Algorithms. | Sriram Govindarajan, Ranga Vemuri |
| 1997 | VLSID | Resource Constrained RTL Partitioning for Synthesis of Multi-FPGA Designs. | Madhavi Vootukuru, Ranga Vemuri, Nand Kumar |
| 1996 | FMCAD | Specification of Control Flow Properties for Verification of Synthesized VHDL Designs. | Naren Narasimhan, Ranga Vemuri |
| 1996 | ISLPED | Simulation based architectural power estimation for PLA-based controllers. | Srinivas Katkoori, Ranga Vemuri |
| 1996 | VLSID | A Hierarchical Register Optimization Algorithm for Behavioral Synthesis. | Srinivas Katkoori, Ranga Vemuri, Jay Roy |
| 1996 | VLSID | Synchronous Controller Models for Synthesis from Communicating VHDL Processes. | Naren Narasimhan, Ranga Vemuri, Jay Roy |
| 1995 | ICCD | High level profiling based low power synthesis technique. | Srinivas Katkoori, Nand Kumar, Ranga Vemuri |
| 1995 | VLSID | Transformations for functional verification of synthesized designs. | William L. Bradley, Ranga Vemuri |
| 1993 | DAC | Performance Specification Using Attributed Grammars. | Ram Mandayam, Ranga Vemuri |
| 1993 | DAC | Experiences in Functional Validation of a High Level Synthesis System. | Ranga Vemuri, Paddy Mamtora, Praveen Sinha, Nand Kumar, Jayanta Roy, Raghu Vutukuru |
| 1992 | DAC | Distributed Design-Space Exploration for High-Level Synthesis Systems. | Rajiv Dutta, Jayanta Roy, Ranga Vemuri |
| 1991 | CAV | Temporal Precondition Verification of Design Transformations. | Ranga Vemuri, Anuradha Sridhar |
| 1986 | MICRO | Data flow graph partitioning to reduce communication cost. | Cris Koutsougeras, Christos A. Papachristou, Ranga Vemuri |
| 1978 | COMPSAC | Continuing education in microprocessors: Use of software simulators. | Ranga Vemuri, J. V. Cornacchio |