| 2018 | TASE | An Improved LLF Scheduling for Reducing Maximum Heap Memory Consumption by Considering Laxity Time. | Yuki Machigashira, Akio Nakata |
| 2006 | DAC | A real time budgeting method for module-level-pipelined bus based system using bus scenarios. | Tadaaki Tanimoto, Seiji Yamaguchi, Akio Nakata, Teruo Higashino |
| 2005 | AINA | Automatic Decomposition of Java Program for Implementation on Mobile Terminals. | Takaaki Umedu, Shigeharu Urata, Akio Nakata, Teruo Higashino |
| 2004 | ATVA | A Global Timed Bisimulation Preserving Abstraction for Parametric Time-Interval Automata. | Tadaaki Tanimoto, Suguru Sasaki, Akio Nakata, Teruo Higashino |
| 2004 | RTSS | A Flexible and High-Reliable HW/SW Co-Design Method for Real-Time Embedded Systems. | Tomoya Kitani, Yoshifumi Takamoto, Keiichi Yasumoto, Akio Nakata, Teruo Higashino |
| 2003 | FPL | Design and Implementation of Priority Queuing Mechanism on FPGA Using Concurrent Periodic EFSMs and Parametric Model Checking. | Tomoya Kitani, Yoshifumi Takamoto, Isao Naka, Keiichi Yasumoto, Akio Nakata, Teruo Higashino |
| 2002 | FM | A Language for Describing Wireless Mobile Applications with Dynamic Establishment of Multi-way Synchronization Channels. | Takaaki Umedu, Yoshiki Terashima, Keiichi Yasumoto, Akio Nakata, Teruo Higashino, Kenichi Taniguchi |
| 2002 | FPL | Design and Implementation of FPGA Circuits for High Speed Network Monitors. | Masayuki Kirimura, Yoshifumi Takamoto, Takanori Mori, Keiichi Yasumoto, Akio Nakata, Teruo Higashino |
| 2001 | FORTE | Deriving Parameter Conditions for Periodic Timed Automata Satisfying Real-Time Temporal Logic Formulas. | Akio Nakata, Teruo Higashino |
| 1998 | RTCSA | Protocol Synthesis from Context-Free Processes Using Event Structures. | Akio Nakata, Teruo Higashino, Kenichi Taniguchi |
| 1996 | FORTE | Time-Action Alternating Model for Timed LOTOS and its Symbolic Verification of Bisimulation Equivalence. | Akio Nakata, Teruo Higashino, Kenichi Taniguchi |
| 1995 | FORTE | Verification of Liveness Property for Communicating FSM's with Conditional Transitions Depending on State Visiting Numbers. | Teruo Higashino, Akio Nakata, Tatsuo Itoh, Kenichi Taniguchi |
| 1995 | ICNP | Protocol synthesis from timed and structured specifications. | Akio Nakata, Teruo Higashino, Kenichi Taniguchi |
| 1993 | FORTE | LOTOS enhancement to specify time constraint among non-adjacent actions using first order logic. | Akio Nakata, Teruo Higashino, Kenichi Taniguchi |