Alexandre Verle
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
3
Venues
2
Active years
2004–2006
Best venue rank
C
Where they publish
Papers
3 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2006 | ISCAS | Circuit sizing method under delay constraint. | Alexandre Verle, A. Landrault, Philippe Maurine, Nadine Azmard |
| 2005 | DATE | Low Power Oriented CMOS Circuit Optimization Protocol. | Alexandre Verle, Xavier Michel, Nadine Azmard, Philippe Maurine, Daniel Auvergne |
| 2004 | ISCAS | Delay bound based CMOS gate sizing technique. | Alexandre Verle, Xavier Michel, Philippe Maurine, Nadine Azmard, Daniel Auvergne |