| 2021 | ASPDAC | A Dynamic Link-latency Aware Cache Replacement Policy (DLRP). | Yen-Hao Chen, Allen C.-H. Wu, TingTing Hwang |
| 2016 | DATE | A novel cache-utilization based dynamic voltage frequency scaling (DVFS) mechanism for reliability enhancements. | Yen-Hao Chen, Yi-Lun Tang, Yi-Yu Liu, Allen C.-H. Wu, TingTing Hwang |
| 2015 | SIGGRAPH | Elastylus: flexible haptic painting stylus. | Ruimin Lyu, Haojie Hao, Wei Chen, Yuan Liu, Feng Wang, Allen C.-H. Wu |
| 2006 | ISCAS | Performance-driven crosstalk elimination at post-compiler level. | Wu-An Kuo, Yi-Ling Chiang, TingTing Hwang, Allen C.-H. Wu |
| 2005 | ISCAS | A power-driven multiplication instruction-set design method for ASIPs. | Wu-An Kuo, TingTing Hwang, Allen C.-H. Wu |
| 2004 | DATE | Decomposition of Instruction Decoder for Low Power Design. | Wu-An Kuo, TingTing Hwang, Allen C.-H. Wu |
| 2003 | DATE | G-MAC: An Application-Specific MAC/Co-Processor Synthesizer. | Alex C.-Y. Chang, Wu-An Kuo, Allen C.-H. Wu, TingTing Hwang |
| 2003 | DATE | A Custom-Cell Identification Method for High-Performance Mixed Standard/Custom-Cell Designs. | Jennifer Y.-L. Lo, Wu-An Kuo, Allen C.-H. Wu, TingTing Hwang |
| 2002 | ISCAS | High-performance FIR generation based on a timing-driven architecture and component selection method. | Jerry C.-Y. Kao, C.-F. Su, Allen C.-H. Wu |
| 2002 | ISCAS | A carry-select-adder optimization technique for high-performance Booth-encoded Wallace-tree multipliers. | M.-J. Liao, C.-F. Su, Alex C.-Y. Chang, Allen C.-H. Wu |
| 2001 | ASPDAC | An RTL design-space exploration method for high-level applications. | Peng-Cheng Kao, Chih-Kuang Hsieh, Allen C.-H. Wu |
| 2000 | ASPDAC | Embedded tutorial: essential issues for IP reuse. | Daniel Gajski, Allen C.-H. Wu, Viraphol Chaiyakul, Shojiro Mori, Tom Nukiyama, Pierre Bricaud |
| 2000 | ICCAD | Delay Budgeting for a Timing-Closure-Driven Design Method. | Chien-Chu Kuo, Allen C.-H. Wu |
| 1999 | ASPDAC | A Multi-Level FPGA Synthesis Method Supporting HDL Debugging for Emulation-Based Designs. | Wen-Jong Fang, Peng-Cheng Kao, Allen C.-H. Wu |
| 1999 | DAC | A Timing-Driven Soft-Macro Resynthesis Method in Interaction with Chip Floorplanning. | Hsiao-Pin Su, Allen C.-H. Wu, Youn-Long Lin |
| 1999 | FPGA | Module Generation of High Performance FPGA-Based Multipliers. | Kun-Ming Ho, Allen C.-H. Wu |
| 1998 | DAC | Performance-Driven Multi-FPGA Partitioning Using Functional Clustering and Replication. | Wen-Jong Fang, Allen C.-H. Wu |
| 1997 | ASPDAC | DP-Gen: a datapath generator for multiple-FPGA applications. | Wen-Jong Fang, Allen C.-H. Wu, Ti-Yen Yen, Tsair-Chin Lin |
| 1997 | ASPDAC | An entropy measure for power estimation of Boolean functions. | Chi-Hong Hwang, Allen C.-H. Wu |
| 1997 | ASPDAC | Evaluating cost-performance tradeoffs for system level applications. | Wei-Liang Ing, Cheng-Tsung Hwang, Allen C.-H. Wu |
| 1997 | DAC | Multi-Way FPGA Partitioning by Fully Exploiting Design Hierarchy. | Wen-Jong Fang, Allen C.-H. Wu |
| 1997 | DAC | A Real-Time RTL Engineering-Change Method Supporting On-Line Debugging for Logic-Emulation Applications. | Wen-Jong Fang, Allen C.-H. Wu, Ti-Yen Yen |
| 1997 | FPGA | Module Generation of Complex Macros for Logic-Emulation Applications. | Wen-Jong Fang, Allen C.-H. Wu, Duan-Ping Chen |
| 1997 | ICCAD | A predictive system shutdown method for energy saving of event-driven computation. | Chi-Hong Hwang, Allen C.-H. Wu |
| 1996 | ICCAD | A hierarchical functional structuring and partitioning approach for multiple-FPGA implementations. | Wen-Jong Fang, Allen C.-H. Wu |
| 1995 | ASPDAC | EMPAR: an interactive synthesis environment for hardware emulations. | Wen-Jong Fang, Allen C.-H. Wu, Tsing-Gen Lee |
| 1995 | DAC | A Performance and Routability Driven Router for FPGAs Considering Path Delays. | Yuh-Sheng Lee, Allen C.-H. Wu |
| 1994 | ICCD | State Assignment for Power and Area Minimization. | Kuo-Hua Wang, Wen-Sing Wang, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin |
| 1993 | ICCAD | Combining technology mapping and placement for delay-optimization in FPGA designs. | Chau-Shen Chen, Yu-Wen Tsay, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin |
| 1992 | ICCAD | An effective methodology for functional pipelining. | Tsing-Fa Lee, Allen C.-H. Wu, Daniel Gajski, Youn-Long Lin |
| 1992 | ICCAD | Accurate layout area and delay modeling for system level design. | Champaka Ramachandran, Fadi J. Kurdahi, Daniel Gajski, Allen C.-H. Wu, Viraphol Chaiyakul |
| 1992 | ICCAD | An efficient multi-view design model for real-time interactive synthesis. | Allen C.-H. Wu, Tedd Hadley, Daniel Gajski |
| 1991 | ICCAD | Layout-Area Models for High-Level Synthesis. | Allen C.-H. Wu, Viraphol Chaiyakul, Daniel Gajski |
| 1990 | ICCAD | Partitioning Algorithms for Layout Synthesis from Register-Transfer Netlists. | Allen C.-H. Wu, Daniel Gajski |