Anand Rajaram
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
8
Venues
4
Active years
2003–2024
Best venue rank
A*
Where they publish
Papers
8 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2024 | DAC | DGR: Differentiable Global Router. | Wei Li, Rongjian Liang, Anthony Agnesina, Haoyu Yang, Chia-Tung Ho, Anand Rajaram, Haoxing Ren |
| 2023 | ASPDAC | BufFormer: A Generative ML Framework for Scalable Buffering. | Rongjian Liang, Siddhartha Nath, Anand Rajaram, Jiang Hu, Haoxing Ren |
| 2009 | DATE | Analysis and optimization of NBTI induced clock skew in gated clock trees. | Ashutosh Chakraborty, Gokul Ganesan, Anand Rajaram, David Z. Pan |
| 2008 | ASPDAC | MeshWorks: An efficient framework for planning, synthesis and optimization of clock mesh networks. | Anand Rajaram, David Z. Pan |
| 2008 | DAC | Robust chip-level clock tree synthesis for SOC designs. | Anand Rajaram, David Z. Pan |
| 2005 | ICCAD | Practical techniques to reduce skew and its variations in buffered clock networks. | Ganesh Venkataraman, Nikhil Jayakumar, Jiang Hu, Peng Li, Sunil P. Khatri, Anand Rajaram, Patrick McGuinness, Charles J. Alpert |
| 2004 | DAC | Reducing clock skew variability via cross links. | Anand Rajaram, Jiang Hu, Rabi N. Mahapatra |
| 2003 | ICCAD | Analytical Bound for Unwanted Clock Skew due to Wire Width Variation. | Anand Rajaram, Bing Lu, Wei Guo, Rabi N. Mahapatra, Jiang Hu |