| 2024 | ASPLOS | PDIP: Priority Directed Instruction Prefetching. | Bhargav Reddy Godala, Sankara Prasad Ramesh, Gilles A. Pokam, Jared Stark, Andr Seznec, Dean M. Tullsen, David I. August |
| 2021 | ICCD | Conciliating Speed and Efficiency on Cache Compressors. | Daniel Rodrigues Carvalho, Andr Seznec |
| 2019 | ICCD | Value Speculation through Equality Prediction. | Kleovoulos Kalaitzidis, Andr Seznec |
| 2019 | SBAC-PAD | Compressed Cache Layout Aware Prefetching. | Niloofar Charmchi, Caroline Collange, Andr Seznec |
| 2017 | CC | Compile-time function memoization. | Arjun Suresh, Erven Rohou, Andr Seznec |
| 2016 | HPCA | Cost effective physical register sharing. | Arthur Perais, Andr Seznec |
| 2016 | MICRO | Dictionary sharing: An efficient cache compression scheme for compressed caches. | Biswabandan Panda, Andr Seznec |
| 2016 | MICRO | Register sharing for equality prediction. | Arthur Perais, Fernando A. Endo, Andr Seznec |
| 2016 | SBAC-PAD | Dynamic Inter-Thread Vectorization Architecture: Extracting DLP from TLP. | Sajith Kalathingal, Caroline Collange, Bharath Narasimha Swamy, Andr Seznec |
| 2015 | CGO | Branch prediction and the performance of interpreters: don't trust folklore. | Erven Rohou, Bharath Narasimha Swamy, Andr Seznec |
| 2015 | HPCA | Prediction-based superpage-friendly TLB designs. | Misel-Myrto Papadopoulou, Xin Tong, Andr Seznec, Andreas Moshovos |
| 2015 | HPCA | BeBoP: A cost effective predictor infrastructure for superscalar value prediction. | Arthur Perais, Andr Seznec |
| 2015 | ISCA | Cost-effective speculative scheduling in high performance processors. | Arthur Perais, Andr Seznec, Pierre Michaud, Andreas Sembrant, Erik Hagersten |
| 2015 | MICRO | Long term parking (LTP): criticality-aware resource allocation in OOO processors. | Andreas Sembrant, Trevor E. Carlson, Erik Hagersten, David Black-Schaffer, Arthur Perais, Andr Seznec, Pierre Michaud |
| 2015 | MICRO | The inner most loop iteration counter: a new dimension in branch history. | Andr Seznec, Joshua San Miguel, Jorge Albericio |
| 2014 | HPCA | Practical data value speculation for future high-end processors. | Arthur Perais, Andr Seznec |
| 2014 | ISCA | EOLE: Paving the way for an effective implementation of value prediction. | Arthur Perais, Andr Seznec |
| 2014 | MICRO | Skewed Compressed Caches. | Somayeh Sardashti, Andr Seznec, David A. Wood |
| 2014 | SBAC-PAD | Impact of Serial Scaling of Multi-threaded Programs in Many-Core Era. | Surya Narayanan, Bharath Narasimha Swamy, Andr Seznec |
| 2014 | SBAC-PAD | Hardware/Software Helper Thread Prefetching on Heterogeneous Many Cores. | Bharath Narasimha Swamy, Alain Ketterlin, Andr Seznec |
| 2013 | CGO | Performance upper bound analysis and optimization of SGEMM on Fermi and Kepler GPUs. | Junjie Lai, Andr Seznec |
| 2013 | ISPASS | Selecting benchmark combinations for the evaluation of multicore throughput. | Ricardo A. Velsquez, Pierre Michaud, Andr Seznec |
| 2012 | RTNS | PRETI: partitioned real-time shared cache for mixed-criticality real-time systems. | Benjamin Lesage, Isabelle Puaut, Andr Seznec |
| 2011 | HPCA | Practical and secure PCM systems by online detection of malicious write streams. | Moinuddin K. Qureshi, Andr Seznec, Luis A. Lastras, Michele Franceschini |
| 2011 | HPCA | Storage free confidence estimation for the TAGE branch predictor. | Andr Seznec |
| 2011 | MICRO | A new case for the TAGE branch predictor. | Andr Seznec |
| 2009 | ICS | Zero-content augmented caches. | Julien Dusser, Thomas Piquet, Andr Seznec |
| 2009 | PPAM | Parallel HAVEGE. | Alin Suciu, Tudor Carean, Andr Seznec, Kinga Marton |
| 2005 | ISCA | Analysis of the O-GEometric History Length Branch Predictor. | Andr Seznec |
| 2004 | CEC | On the design of state-of-the-art pseudorandom number generators by means of genetic programming. | Julio Csar Hernndez Castro, Andr Seznec, Pedro Isasi |
| 2004 | EuroPar | Topic 8: Parallel Computer Architecture and Instruction-Level Parallelism. | Kemal Ebcioglu, Wolfgang Karl, Andr Seznec, Marco Aldinucci |
| 2004 | ICCSA | The SAC Test: A New Randomness Test, with Some Applications to PRNG Analysis. | Julio Csar Hernndez Castro, Jos Mara Sierra, Andr Seznec |
| 2004 | SBAC-PAD | IATO: A Flexible EPIC Simulation Environment. | Amaury Darsch, Andr Seznec |
| 2003 | ISCA | Effective ahead Pipelining of Instruction Block Address Generation. | Andr Seznec, Antony Fraboulet |
| 2002 | ISCA | Tarantula: A Vector Extension to the Alpha Architecture. | Roger Espasa, Federico Ardanaz, Julio Gago, Roger Gramunt, Isaac Hernandez, Toni Juan, Joel S. Emer, Stephen Felix, P. Geoffrey Lowney, Matthew Mattina, Andr Seznec |
| 2002 | ISCA | Design Tradeoffs for the Alpha EV8 Conditional Branch Predictor. | Andr Seznec, Stephen Felix, Venkata Krishnan, Yiannakis Sazeides |
| 2002 | MICRO | Register write specialization register read specialization: a path to complexity-effective wide-issue superscalar processors. | Andr Seznec, Eric Toullec, Olivier Rochecouste |
| 2001 | EuroPar | Topic 08+13: Instruction-Level Parallelism and Computer Architecture. | Eduard Ayguad, Fredrik Dahlgren, Christine Eisenbeis, Roger Espasa, Guang R. Gao, Henk L. Muller, Rizos Sakellariou, Andr Seznec |
| 2001 | HPCA | Data-Flow Prescheduling for Large Instruction Windows in Out-of-Order Processors. | Pierre Michaud, Andr Seznec |
| 2000 | EuroPar | Combining Light Static Code Annotation and Instruction-Set Emulation for Flexible and Efficient On-the-Fly Simulation (Research Note). | Thierry Lafage, Andr Seznec |
| 1999 | EuroPar | OCEANS - Optimising Compilers for Embedded Applications. | Michel Barreteau, Franois Bodin, Zbigniew Chamski, Henri-Pierre Charles, Christine Eisenbeis, John R. Gurd, Jan Hoogerbrugge, Ping Hu, William Jalby, Toru Kisuki, Peter M. W. Knijnenburg, Paul van der Mark, Andy Nisbet, Michael F. P. O'Boyle, Erven Rohou, Andr Seznec, Elena Sthr, Menno Treffers, Harry A. G. Wijshoff |
| 1999 | EuroPar | Code Cloning Tracing: A "Pay per Trace" Approach. | Thierry Lafage, Andr Seznec, Erven Rohou, Franois Bodin |
| 1999 | HPCA | Out-of-Order Execution may not be Cost-Effective on Processors Featuring Simultaneous Multithreading. | Sbastien Hily, Andr Seznec |
| 1998 | EuroPar | OCEANS: Optimising Compilers for Embedded Applications. | Michel Barreteau, Franois Bodin, Peter Brinkhaus, Zbigniew Chamski, Henri-Pierre Charles, Christine Eisenbeis, John R. Gurd, Jan Hoogerbrugge, Ping Hu, William Jalby, Peter M. W. Knijnenburg, Michael F. P. O'Boyle, Erven Rohou, Rizos Sakellariou, Andr Seznec, Elena Sthr, Menno Treffers, Harry A. G. Wijshoff |
| 1997 | EuroPar | OCEANS: Optimizing Compilers for Embedded Applications. | Bas Aarts, Michel Barreteau, Franois Bodin, Peter Brinkhaus, Zbigniew Chamski, Henri-Pierre Charles, Christine Eisenbeis, John R. Gurd, Jan Hoogerbrugge, Ping Hu, William Jalby, Peter M. W. Knijnenburg, Michael F. P. O'Boyle, Erven Rohou, Rizos Sakellariou, Henk Schepers, Andr Seznec, Elena Sthr, Marco Verhoeven, Harry A. G. Wijshoff |
| 1997 | ISCA | Trading Conflict and Capacity Aliasing in Conditional Branch Predictors. | Pierre Michaud, Andr Seznec, Richard Uhlig |
| 1996 | ASPLOS | Multiple-Block Ahead Branch Predictors. | Andr Seznec, Stphan Jourdan, Pascal Sainrat, Pierre Michaud |
| 1996 | ISCA | Don't Use the Page Number, But a Pointer To It. | Andr Seznec |
| 1995 | HPCA | DASC Cache. | Andr Seznec |
| 1995 | ISCA | Skewed Associativity Enhances Performance Predictability. | Franois Bodin, Andr Seznec |
| 1994 | ISCA | Decoupled Sectored Caches: Conciliating Low Tag Implementation Cost and Low Miss Ratio. | Andr Seznec |
| 1993 | ICCD | About Set and Skewed Associativity on Second-Level Caches. | Andr Seznec |
| 1993 | ICPP | Semi-Unified Caches. | Nathalie Drach, Andr Seznec |
| 1993 | ISCA | A Case for Two-Way Skewed-Associative Caches. | Andr Seznec |
| 1993 | ISCA | Odd Memory Systems May be Quite Interesting. | Andr Seznec, Jacques Lenfant |
| 1993 | MICRO | MIDEE: smoothing branch and instruction cache miss penalties on deep pipelines. | Nathalie Drach, Andr Seznec |
| 1992 | ISCA | OPAC: A floating-point coprocessor dedicated to compute-bound kernels. | Andr Seznec, Karl Courtel |
| 1992 | ISCA | Interleaved Parallel Schemes: Improving Memory Throughput on Supercomputers. | Andr Seznec, Jacques Lenfant |
| 1992 | MICRO | Controlling and sequencing a heavily pipelined floating-point operator. | Andr Seznec, Karl Courtel |
| 1989 | ICS | A asynchronous buffering network for tightly coupled multiprocessors. | Yvon Jgou, Andr Seznec |
| 1988 | ISCA | Synchronizing Processors Through Memory Requests in a Tightly Coupled Multiprocessor. | Andr Seznec, Yvon Jgou |
| 1988 | ICS | Towards a large number of pipeline processors in a tightly coupled multiprocessor using no cache. | Andr Seznec, Yvon Jgou |
| 1987 | ICPP | Optimizing Memory Throughput In a Tightly Coupled Multiprocessor. | Andr Seznec, Yvon Jgou |
| 1986 | ICPP | Data Synchronized Pipeline Architecture: Pipelining in Multiprocessor Environments. | Yvon Jgou, Andr Seznec |
| 1986 | ISCA | An Efficient Routing Control Unit for the SIGMA Network E(4). | Andr Seznec |