| 2016 | ASPDAC | Design and verification using high-level synthesis. | Andrs Takach |
| 2010 | ASPDAC | Minimizing leakage power in aging-bounded high-level synthesis with design time multi- | Yibo Chen, Yuan Xie, Yu Wang, Andrs Takach |
| 2010 | ASPDAC | Parametric yield driven resource binding in behavioral synthesis with multi- | Yibo Chen, Yuan Xie, Yu Wang, Andrs Takach |
| 2009 | ASPDAC | Variation-aware resource sharing and binding in behavioral synthesis. | Feng Wang, Yuan Xie, Andrs Takach |
| 2009 | DAC | From milliwatts to megawatts: system level power challenge. | Ruchir Puri, Eshel Haritan, Stan Krolikoski, Jason Cong, Tim Kogel, Bradley D. McCredie, John Shen, Andrs Takach |
| 2005 | DATE | C Based Hardware Design for Wireless Applications. | Andrs Takach, Bryan Bowyer, Thomas Bollaert |
| 2005 | FDL | C-Based Hardware Design for Wireless Applications . | Andrs Takach, Bryan Bowyer, Thomas Bollaert |
| 2004 | FDL | Fast Bit-Accurate C++ Datatypes For Functional System Verification and Synthesis. | Andrs Takach, Simon Waters, Peter Gutberlet |
| 1992 | DAC | The Princeton University Behavioral Synthesis System. | Wayne H. Wolf, Andrs Takach, Chun-Yao Huang, Richard Manno, Ephrem Wu |