Antonio Pullini
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
14
Venues
6
Active years
2007–2021
Best venue rank
A*
Where they publish
Papers
14 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2021 | DATE | MemPool: A Shared-L1 Memory Many-Core Cluster with a Low-Latency Interconnect. | Matheus A. Cavalcante, Samuel Riedel, Antonio Pullini, Luca Benini |
| 2019 | ISCAS | An Energy Efficient System for Touch Modality Classification in Electronic Skin Applications. | Mario Osta, Ali Ibrahim, Michele Magno, Manuel Eggimann, Antonio Pullini, Paolo Gastaldo, Maurizio Valle |
| 2018 | ISCAS | Live Demonstration: Body-Bias Based Performance Monitoring and Compensation for a Near-Threshold Multi-Core Cluster in 28nm FD-SOI Technology. | Alfio Di Mauro, Davide Rossi, Antonio Pullini, Philippe Flatresse, Luca Benini |
| 2016 | ISCAS | A heterogeneous multi-core system-on-chip for energy efficient brain inspired vision. | Antonio Pullini, Francesco Conti, Davide Rossi, Igor Loi, Michael Gautschi, Luca Benini |
| 2015 | HPCA | Exploring architectural heterogeneity in intelligent vision systems. | Nandhini Chandramoorthy, Giuseppe Tagliavini, Kevin M. Irick, Antonio Pullini, Siddharth Advani, Sulaiman Al Habsi, Matthew Cotter, John Sampson, Vijaykrishnan Narayanan, Luca Benini |
| 2014 | CVPR | Brain-Inspired Classroom Occupancy Monitoring on a Low-Power Mobile Platform. | Francesco Conti, Antonio Pullini, Luca Benini |
| 2010 | DAC | Networks on Chips: from research to products. | Giovanni De Micheli, Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Federico Angiolini, Antonio Pullini |
| 2010 | ISCAS | 3D NoCs - Unifying inter & intra chip communication. | Igor Loi, Pol Marchal, Antonio Pullini, Luca Benini |
| 2010 | ISLPED | Automatic synthesis of near-threshold circuits with fine-grained performance tunability. | Mohammad Reza Kakoee, Ashoka Visweswara Sathanur, Antonio Pullini, Jos Huisken, Luca Benini |
| 2009 | DATE | Design of compact imperfection-immune CNFET layouts for standard-cell-based logic synthesis. | Shashikanth Bobba, Jie Zhang, Antonio Pullini, David Atienza, Giovanni De Micheli |
| 2009 | DATE | Physically clustered forward body biasing for variability compensation in nanometer CMOS design. | Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Giovanni De Micheli, Enrico Macii |
| 2008 | DATE | A Scalable Algorithmic Framework for Row-Based Power-Gating. | Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino |
| 2008 | ISCAS | On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits. | Ashoka Visweswara Sathanur, Andrea Calimera, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino |
| 2007 | ISLPED | Timing-driven row-based power gating. | Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino |