| 2025 | ASPDAC | DEMOTIC: A Differentiable Sampler for Multi-Level Digital Circuits. | Arash Ardakani, Minwoo Kang, Kevin He, Qijing Huang, Vighnesh M. Iyer, Suhong Moon, John Wawrzynek |
| 2025 | DATE | High-Throughput SAT Sampling. | Arash Ardakani, Minwoo Kang, Kevin He, Qijing Huang, John Wawrzynek |
| 2024 | DAC | Late Breaking Results: Differential and Massively Parallel Sampling of SAT Formulas. | Arash Ardakani, Minwoo Kang, Kevin He, Vighnesh M. Iyer, Suhong Moon, John Wawrzynek |
| 2024 | NAACL | SlimFit: Memory-Efficient Fine-Tuning of Transformer-based Models Using Training Dynamics. | Arash Ardakani, Altan Haan, Shangyin Tan, Doru-Thom Popovici, Alvin Cheung, Costin Iancu, Koushik Sen |
| 2022 | EMNLP | Partially-Random Initialization: A Smoking Gun for Binarization Hypothesis of BERT. | Arash Ardakani |
| 2020 | ISCAS | A Regression-Based Method to Synthesize Complex Arithmetic Computations on Stochastic Streams. | Arash Ardakani, Amir Ardakani, Warren J. Gross |
| 2019 | DATE | Learning to Skip Ineffectual Recurrent Computations in LSTMs. | Arash Ardakani, Zhengyun Ji, Warren J. Gross |
| 2019 | ICLR | Learning Recurrent Binary/Ternary Weights. | Arash Ardakani, Zhengyun Ji, Sean C. Smithson, Brett H. Meyer, Warren J. Gross |
| 2018 | ISCAS | A Convolutional Accelerator for Neural Networks With Binary Weights. | Arash Ardakani, Carlo Condo, Warren J. Gross |
| 2017 | ICLR | Sparsely-Connected Neural Networks: Towards Efficient VLSI Implementation of Deep Neural Networks. | Arash Ardakani, Carlo Condo, Warren J. Gross |
| 2017 | ISCAS | A low-complexity fully scalable interleaver/address generator based on a novel property of QPP interleavers. | Arash Ardakani, Mahdi Shabany |
| 2016 | ICASSP | Hardware implementation of FIR/IIR digital filters using integral stochastic computation. | Arash Ardakani, Franois Leduc-Primeau, Warren J. Gross |
| 2015 | ISCAS | An efficient max-log MAP algorithm for VLSI implementation of turbo decoders. | Arash Ardakani, Mahdi Shabany |
| 2013 | ISCAS | An efficient VLSI architecture of QPP interleaver/deinterleaver for LTE turbo coding. | Arash Ardakani, Mojtaba Mahdavi, Mahdi Shabany |