| 2019 | CCS | VeriSketch: Synthesizing Secure Hardware Designs with Timing-Sensitive Information Flow Properties. | Armaiti Ardeshiricham, Yoshiki Takashima, Sicun Gao, Ryan Kastner |
| 2018 | DATE | Examining the consequences of high-level synthesis optimizations on power side-channel. | Lu Zhang, Wei Hu, Armaiti Ardeshiricham, Yu Tai, Jeremy Blackstone, Dejun Mu, Ryan Kastner |
| 2018 | ICCAD | Property specific information flow analysis for hardware security verification. | Wei Hu, Armaiti Ardeshiricham, Mustafa S. Gobulukoglu, Xinmu Wang, Ryan Kastner |
| 2017 | DATE | Register transfer level information flow tracking for provably secure hardware design. | Armaiti Ardeshiricham, Wei Hu, Joshua Marxen, Ryan Kastner |
| 2017 | ICCAD | Clepsydra: Modeling timing flows in hardware designs. | Armaiti Ardeshiricham, Wei Hu, Ryan Kastner |
| 2017 | ICCAD | Why you should care about don't cares: Exploiting internal don't care conditions for hardware Trojans. | Wei Hu, Lu Zhang, Armaiti Ardeshiricham, Jeremy Blackstone, Bochuan Hou, Yu Tai, Ryan Kastner |