| 2023 | ARITH | Using Hierarchical Approach to Speed-up RNS Base Extensions in Homomorphic Encryption Context. | Morgane Vollmer, Karim Bigou, Arnaud Tisserand |
| 2022 | DDECS | Processor Extensions for Hardware Instruction Replay against Fault Injection Attacks. | Noura Ait Manssour, Vianney Laptre, Guy Gogniat, Arnaud Tisserand |
| 2019 | ARITH | Hierarchical Approach in RNS Base Extension for Asymmetric Cryptography. | Libey Djath, Karim Bigou, Arnaud Tisserand |
| 2019 | INDOCRYPT | FPGA Implementation and Comparison of Protections Against SCAs for RLWE. | Timo Zijlstra, Karim Bigou, Arnaud Tisserand |
| 2017 | ACSSC | Hyper-threaded multiplier for HECC. | Gabriel Gallin, Arnaud Tisserand |
| 2017 | INDOCRYPT | Architecture Level Optimizations for Kummer Based HECC on FPGAs. | Gabriel Gallin, Trk zlm elik, Arnaud Tisserand |
| 2016 | ARITH | Hybrid Position-Residues Number System. | Karim Bigou, Arnaud Tisserand |
| 2015 | CHES | Single Base Modular Multiplication for Efficient Hardware RNS Implementations of ECC. | Karim Bigou, Arnaud Tisserand |
| 2015 | DSD | Fast and Secure Finite Field Multipliers. | Danuta Pamula, Arnaud Tisserand |
| 2013 | ARITH | On-the-Fly Multi-base Recoding for ECC Scalar Multiplication without Pre-computations. | Thomas Chabrier, Arnaud Tisserand |
| 2013 | CHES | Improving Modular Inversion in RNS Using the Plus-Minus Method. | Karim Bigou, Arnaud Tisserand |
| 2012 | WAIFI | $\textrm{GF}(2^m)$ Finite-Field Multipliers with Reduced Activity Variations. | Danuta Pamula, Arnaud Tisserand |
| 2011 | FPL | A Comparison on FPGA of Modular Multipliers Suitable for Elliptic Curve Cryptography over GF(p) for Specific p Values. | Mark Hamilton, William P. Marnane, Arnaud Tisserand |
| 2009 | ICCS | Power Consumption of GPUs from a Software Perspective. | Caroline Collange, David Defour, Arnaud Tisserand |
| 2008 | ACSSC | Fast and accurate activity evaluation in multipliers. | Arnaud Tisserand |
| 2008 | FDTC | Error Detection for Borrow-Save Adders Dedicated to ECC Unit. | Julien Francq, Jean-Baptiste Rigaud, Pascal Manet, Assia Tria, Arnaud Tisserand |
| 2006 | ICASSP | Hardware Operator for Simultaneous Sine and Cosine Evaluation. | Arnaud Tisserand |
| 2005 | ARITH | Division by Constant for the ST100 DSP Microprocessor. | Jean-Michel Muller, Arnaud Tisserand, Benot Dupont de Dinechin, Christophe Monat |
| 2003 | ARITH | Some Optimizations of Hardware Multiplication by Constant Matrices. | Nicolas Boullis, Arnaud Tisserand |
| 2002 | FPL | Small Multiplier-Based Multiplication and Division Operators for Virtex-II Devices. | Jean-Luc Beuchat, Arnaud Tisserand |
| 2001 | ARITH | Some Improvements on Multipartite Table Methods . | Florent de Dinechin, Arnaud Tisserand |
| 1999 | FPL | An On-Line Arithmetic Based FPGA for Low-Power Custom Computing. | Arnaud Tisserand, Pierre Marchal, Christian Piguet |
| 1997 | ARITH | Towards Correctly Rounded Transcendentals. | Vincent Lefvre, Arnaud Tisserand, Jean-Michel Muller |
| 1997 | FPL | FPGA implementation of real-time digital controllers using on-line arithmetic. | Arnaud Tisserand, Martin Dimmler |
| 1995 | ARITH | Semi-Logarithmic Number Systems. | Jean-Michel Muller, Arnaud Tisserand, Alexandre Scherbyna |