Ashoka Visweswara Sathanur
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
10
Venues
3
Active years
2006–2010
Best venue rank
A
Where they publish
Papers
10 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2010 | ISLPED | Automatic synthesis of near-threshold circuits with fine-grained performance tunability. | Mohammad Reza Kakoee, Ashoka Visweswara Sathanur, Antonio Pullini, Jos Huisken, Luca Benini |
| 2009 | DATE | Physically clustered forward body biasing for variability compensation in nanometer CMOS design. | Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Giovanni De Micheli, Enrico Macii |
| 2008 | DATE | A Scalable Algorithmic Framework for Row-Based Power-Gating. | Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino |
| 2008 | ISCAS | On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits. | Ashoka Visweswara Sathanur, Andrea Calimera, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino |
| 2008 | ISLPED | Multiple power-gating domain (multi-VGND) architecture for improved leakage power reduction. | Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino |
| 2007 | DATE | Interactive presentation: Efficient computation of discharge current upper bounds for clustered sleep transistor sizing. | Ashoka Visweswara Sathanur, Andrea Calimera, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino |
| 2007 | ISCAS | Design Exploration of a Thermal Management Unit for Dynamic Control of Temperature-Induced Clock Skew. | Karthik Duraisami, Prassanna Sithambaram, Ashoka Visweswara Sathanur, Alberto Macii, Enrico Macii, Massimo Poncino |
| 2007 | ISLPED | Timing-driven row-based power gating. | Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino |
| 2006 | ISCAS | Implications of ultra low-voltage devices on design techniques for controlling leakage in NanoCMOS circuits. | Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Alberto Macii, Enrico Macii, Massimo Poncino |
| 2006 | ISLPED | Dynamic thermal clock skew compensation using tunable delay buffers. | Ashutosh Chakraborty, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino |