Skip to content

Astrit Ademaj

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

10

Venues

8

Active years

2002–2017

Best venue rank

C

Where they publish

Papers

10 indexed papers, newest first.

YearVenueTitleAuthors
2017ETFASelf-configuration of IEEE 802.1 TSN networks.Marina Gutirrez, Astrit Ademaj, Wilfried Steiner, Radu Dobrin, Sasikumar Punnekkat
2008ETFASegmentation of standard ethernet messages in the time-triggered ethernet.Vaclav Mikolasek, Astrit Ademaj, Stanislav Racek
2007DSNA Tunable Add-On Diagnostic Protocol for Time-Triggered Systems.Marco Serafini, Neeraj Suri, Jonny Vinter, Astrit Ademaj, Wolfgang Brandsttter, Fulvio Tagliabo, Jens Koch
2007SAFECOMPExperimental Evaluation of the DECOS Fault-Tolerant Communication Layer.Jonny Vinter, Henrik Eriksson, Astrit Ademaj, Bernhard Leiner, Martin Schlager
2006DATEA time-triggered ethernet (TTE) switch.Klaus Steinhammer, Petr Grillinger, Astrit Ademaj, Hermann Kopetz
2005ISORCThe Time-Triggered Ethernet (TTE) Design.Hermann Kopetz, Astrit Ademaj, Petr Grillinger, Klaus Steinhammer
2004RTSSIntegration of Internal and External Clock Synchronization by the Combination of Clock-State and Clock-Rate Correction in Fault-Tolerant Distributed Systems.Hermann Kopetz, Astrit Ademaj, Alexander Hanzlik
2003DSNEvaluation of Fault Handling of the Time-Triggered Architecture with Bus and Star Topology.Astrit Ademaj, Hkan Sivencrona, Gnther Bauer, Jan Torin
2002EDCCA Methodology for Dependability Evaluation of the Time-Triggered Architecture Using Software Implemented Fault Injection.Astrit Ademaj
2002IOLTSFault Tolerance Evaluation Using Two Software Based Fault Injection Methods.Astrit Ademaj, Petr Grillinger, Pavel Herout, Jan Hlavicka