Atsushi Kawasumi
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
3
Venues
3
Active years
2002–2012
Best venue rank
A
Where they publish
Papers
3 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2012 | ISLPED | A 40-nm 256-Kb Sub-10 pJ/Access 8t SRAM with read bitline amplitude limiting (RBAL) scheme. | Shusuke Yoshimoto, Masaharu Terada, Youhei Umeki, Shunsuke Okumura, Atsushi Kawasumi, Toshikazu Suzuki, Shinichi Moriwaki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto |
| 2005 | ICCAD | The circuit design of the synergistic processor element of a CELL processor. | Osamu Takahashi, Russ Cook, Scott R. Cottier, Sang H. Dhong, Brian K. Flachs, Koji Hirairi, Atsushi Kawasumi, Hiroaki Murakami, Hiromi Noro, Hwa-Joon Oh, S. Onish, Juergen Pille, Joel Silberman |
| 2002 | ITC | DFT Techniques for Wafer-Level At-Speed Testing of High-Speed SRAMs. | Osamu Hirabayashi, Azuma Suzuki, Tomoaki Yabe, Atsushi Kawasumi, Yasuhisa Takeyama, Keiichi Kushida, Akihito Tohata, Nobuaki Otsuka |