| 2000 | CASES | Efficient design space exploration in PICO. | Santosh G. Abraham, B. Ramakrishna Rau |
| 2000 | CASES | The era of embedded computing. | B. Ramakrishna Rau |
| 2000 | HiPC | Embedded Computing: New Directions in Architecture and Automation. | B. Ramakrishna Rau, Michael S. Schlansker |
| 1996 | MICRO | Profile-driven Instruction Level Parallel Scheduling with Application to Super Blocks. | Chandra Chekuri, Richard Johnson, Rajeev Motwani, B. Natarajan, B. Ramakrishna Rau, Michael S. Schlansker |
| 1996 | MICRO | Optimization of Machine Descriptions for Efficient Use. | John C. Gyllenhaal, Wen-mei W. Hwu, B. Ramakrishna Rau |
| 1995 | MICRO | Region-based compilation: an introduction and motivation. | Richard E. Hank, Wen-mei W. Hwu, B. Ramakrishna Rau |
| 1994 | MICRO | Iterative modulo scheduling: an algorithm for software pipelining loops. | B. Ramakrishna Rau |
| 1993 | MICRO | Predictability of load/store instruction latencies. | Santosh G. Abraham, Rabin A. Sugumar, Daniel Windheiser, B. Ramakrishna Rau, Rajiv Gupta |
| 1993 | MICRO | Dynamically scheduled VLIW processors. | B. Ramakrishna Rau |
| 1993 | PLDI | Reverse If-Conversion. | Nancy J. Warter, Scott A. Mahlke, Wen-mei W. Hwu, B. Ramakrishna Rau |
| 1992 | ASPLOS | Sentinel Scheduling for VLIW and Superscalar Processors. | Scott A. Mahlke, William Y. Chen, Wen-mei W. Hwu, B. Ramakrishna Rau, Michael S. Schlansker |
| 1992 | MICRO | Code generation schema for modulo scheduled loops. | B. Ramakrishna Rau, Michael S. Schlansker, Parthasarathy P. Tirumalai |
| 1992 | PLDI | Register Allocation for Software Pipelined Loops. | B. Ramakrishna Rau, Meng Lee, Parthasarathy P. Tirumalai, Michael S. Schlansker |
| 1991 | ISCA | Pseudo-Randomly Interleaved Memory. | B. Ramakrishna Rau |
| 1989 | ICPP | The Cydram 5 Stride-Insensitive Memory System. | B. Ramakrishna Rau, Michael S. Schlansker, David W. L. Yen |
| 1982 | ASPLOS | Architectural Support for the Efficient Generation of Code for Horizontal Architectures. | B. Ramakrishna Rau, Christopher D. Glaeser, E. M. Greenawalt |
| 1982 | ISCA | Efficient code generation for horizontal architectures: Compiler techniques and architectural support. | B. Ramakrishna Rau, Christopher D. Glaeser, Raymond L. Picard |
| 1981 | MICRO | Some scheduling techniques and an easily schedulable horizontal architecture for high performance scientific computing. | B. Ramakrishna Rau, Christopher D. Glaeser |
| 1978 | MICRO | Levels of representation of programs and the architecture of universal host machines. | B. Ramakrishna Rau |
| 1977 | ISCA | The Effect of Instruction Fetch Strategies upon the Performance of Pipelined Instruction Units. | B. Ramakrishna Rau, George E. Rossman |
| 1976 | DAC | A new philosophy for interconnection on multilayer boards. | B. Ramakrishna Rau |