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Baher Haroun

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

10

Venues

4

Active years

1988–2023

Best venue rank

C

Where they publish

Papers

10 indexed papers, newest first.

Year	Venue	Title	Authors
2023	ISCAS	High-Linearity High-Bandwidth (>20GHz) T&H Front Ends Using Active Bootstrapping and Heterogeneous SiGe/CMOS Circuit Co-Design.	Athanasios Ramkaj, Michael Perrott, Baher Haroun, Boris Murmann
1995	FPGA	Synthesis of Signal Processing Structured Datapaths for FPGAs Supporting RAMs and Busses.	Baher Haroun, Behzad Sajjadi
1995	ISCAS	Floorplanning with Datapath Optimization.	Abdelhakim Safir, Baher Haroun, Krishnaiyan Thulasiraman
1994	ICCD	Optimal Datapath Synthesis of Partitioned Signal Processing Algorithm for Multiple FPGAs.	Baher Haroun, Behzard Sajjadi
1994	ISCAS	A Novel Reduced Swing CMOS Bus Interface Circuit for High Speed Low Power VLSI Systems.	Reza Golshan, Baher Haroun
1994	ISCAS	A Two Stage Structure for High Order Multi-Bit Sigma-Delta ADC with Multiplier-less Digital Correction Logic.	Baher Haroun, Chao Hua Wu
1994	ISCAS	A Floorplanner driven by Structural & Timing Constraints.	Abdelhakim Safir, Baher Haroun, Krishnaiyan Thulasiraman
1992	ICCAD	Power estimation tool for sub-micron CMOS VLSI circuits.	F. Rouatbi, Baher Haroun, Asim J. Al-Khalili
1992	ICCD	Synthesis of Multiple Bus/Functional Unit Architectures Implementing Neural Networks.	Baher Haroun, Elie Torbey
1988	ICCAD	Automatic synthesis of a multi-bus architecture for DSP.	Baher Haroun, Mohamed I. Elmasry