| 2008 | EUC | Advanced Optimization and Design Issues of a 32-Bit Embedded Processor Based on Produced Order Queue Computation Model. | Hiroki Hoshino, Ben A. Abderazek, Kenichi Kuroda |
| 2008 | EUC | Single Instruction Dual-Execution Model Processor Architecture. | Taichi Maekawa, Ben A. Abderazek, Kenichi Kuroda |
| 2007 | EUC | An Efficient Code Generation Algorithm for Code Size Reduction Using 1-Offset P-Code Queue Computation Model. | Arquimedes Canedo, Ben A. Abderazek, Masahiro Sowa |
| 2007 | PDCAT | New Code Generation Algorithm for QueueCore - An Embedded Processor with High ILP. | Arquimedes Canedo, Ben A. Abderazek, Masahiro Sowa |
| 2007 | SBAC-PAD | Queue Register File Optimization Algorithm for QueueCore Processor. | Arquimedes Canedo, Ben A. Abderazek, Masahiro Sowa |
| 2006 | ISPA | On the Design of a Dual-Execution Modes Processor: Architecture and Preliminary Evaluation. | Md. Musfiquzzaman Akanda, Ben A. Abderazek, Masahiro Sowa |
| 2005 | EUC | Modular Design Structure and High-Level Prototyping for Novel Embedded Processor Core. | Ben A. Abderazek, Sotaro Kawata, Tsutomu Yoshinaga, Masahiro Sowa |
| 2005 | EUC | An Efficient Dynamic Switching Mechanism (DSM) for Hybrid Processor Architecture. | Md. Musfiquzzaman Akanda, Ben A. Abderazek, Sotaro Kawata, Masahiro Sowa |
| 2003 | ISPA | On the Design of a Register Queue Based Processor Architecture (FaRM-rq). | Ben A. Abderazek, Soichi Shigeta, Tsutomu Yoshinaga, Masahiro Sowa |