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Benot Dupont de Dinechin

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

29

Venues

18

Active years

1991–2025

Best venue rank

A*

Where they publish

Papers

29 indexed papers, newest first.

YearVenueTitleAuthors
2025ARITHDouble-Word Decomposition in a Combined FP16, BF16 and FP32 Dot Product Add Operator.Organe Desrentes, Benot Dupont de Dinechin, Florent de Dinechin
2025HPCAArchitecting Value Prediction around In-Order Execution.Pierre Ravenel, Arthur Perais, Benot Dupont de Dinechin, Frdric Ptrot
2023ARITHExact Fused Dot Product Add Operators.Organe Desrentes, Benot Dupont de Dinechin, Florent de Dinechin
2023DSDExact Dot Product Accumulate Operators for 8-bit Floating-Point Deep Learning.Organe Desrentes, Benot Dupont de Dinechin, Julien Le Maire
2020RTSSA study of predictable execution models implementation for industrial data-flow applications on a multi-core platform with shared banked memory.Matheus Schuh, Claire Maiza, Jol Goossens, Pascal Raymond, Benot Dupont de Dinechin
2019DACConsolidating High-Integrity, High-Performance, and Cyber-Security Functions on a Manycore Processor.Benot Dupont de Dinechin
2019RTNSResponse time analysis of dataflow applications on a many-core processor with shared-memory and network-on-chip.Amaury Graillat, Claire Maiza, Matthieu Moy, Pascal Raymond, Benot Dupont de Dinechin
2018DATEParallel code generation of synchronous programs for a many-core architecture.Amaury Graillat, Matthieu Moy, Pascal Raymond, Benot Dupont de Dinechin
2017DSDPaving the Way Towards a Highly Energy-Efficient and Highly Integrated Compute Node for the Exascale Revolution: The ExaNoDe Approach.Alvise Rigo, Christian Pinto, Kevin Pouget, Daniel Raho, Denis Dutoit, Pierre-Yves Martinez, Chris Doran, Luca Benini, Iakovos Mavroidis, Manolis Marazakis, Valeria Bartsch, Guy Lonsdale, Antoniu Pop, John Goodacre, Annaik Colliot, Paul M. Carpenter, Petar Radojkovic, Dirk Pleiter, Dominique Drouin, Benot Dupont de Dinechin
2017IPCCCImproving 3D lattice boltzmann method stencil with asynchronous transfers on many-core processors.Minh Quan Ho, Christian Obrecht, Bernard Tourancheau, Benot Dupont de Dinechin, Julien Hascoet
2017MICROFeed-Forward Routing for the Wormhole Switching Network-on-Chip of the Kalray MPPA2 Processor.Benot Dupont de Dinechin, Amaury Graillat
2016DACOptimal and fast throughput evaluation of CSDF.Bruno Bodin, Alix Munier Kordon, Benot Dupont de Dinechin
2014CCUsing the SSA-Form in a Code Generator.Benot Dupont de Dinechin
2014DATETime-critical computing on a single-chip massively parallel processor.Benot Dupont de Dinechin, Duco van Amstel, Marc Poulhis, Guillaume Lager
2014MICROGuaranteed Services of the NoC of a Manycore Processor.Benot Dupont de Dinechin, Yves Durand, Duco van Amstel, Alexandre Ghiti
2013ICCSExtended Cyclostatic Dataflow Program Compilation and Execution for an Integrated Manycore Processor.Pascal Aubry, Pierre-Edouard Beaucamps, Frdric Blanc, Bruno Bodin, Sergiu Carpov, Loc Cudennec, Vincent David, Philippe Dore, Paul Dubrulle, Benot Dupont de Dinechin, Franois Galea, Thierry Goubier, Michel Harrand, Samuel Jones, Jean-Denis Lesage, Stphane Louise, Nicolas Morey Chaisemartin, Thanh-Hai Nguyen, Xavier Raynaud, Renaud Sirdey
2013ICCSA Distributed Run-Time Environment for the Kalray MPPABenot Dupont de Dinechin, Pierre Guironnet de Massas, Guillaume Lager, Clment Lger, Benjamin Orgogozo, Jrme Reybert, Thierry Strudel
2011ACSSCA mixed-precision fused multiply and add.Nicolas Brunie, Florent de Dinechin, Benot Dupont de Dinechin
2011APLASA Non-iterative Data-Flow Algorithm for Computing Liveness Sets in Strict SSA Programs.Benoit Boissinot, Florian Brandner, Alain Darte, Benot Dupont de Dinechin, Fabrice Rastello
2009CGORevisiting Out-of-SSA Translation for Correctness, Code Quality and Efficiency.Benoit Boissinot, Alain Darte, Fabrice Rastello, Benot Dupont de Dinechin, Christophe Guillon
2008CGOFast liveness checking for ssa-form programs.Benoit Boissinot, Sebastian Hack, Daniel Grund, Benot Dupont de Dinechin, Fabrice Rastello
2008EuroParInter-block Scoreboard Scheduling in a JIT Compiler for VLIW Processors.Benot Dupont de Dinechin
2006EuroParSCAN: A Heuristic for Near-Optimal Software Pipelining.Florent Blachot, Benot Dupont de Dinechin, Guillaume Huard
2005ARITHDivision by Constant for the ST100 DSP Microprocessor.Jean-Michel Muller, Arnaud Tisserand, Benot Dupont de Dinechin, Christophe Monat
2000CASESCode generator optimizations for the ST120 DSP-MCU core.Benot Dupont de Dinechin, Franois de Ferrire, Christophe Guillon, Artour Stoutchinin
1999CCExtending Modulo Scheduling with Memory Reference Merging.Benot Dupont de Dinechin
1997PACTA Unified Software Pipeline Construction Scheme for Modulo Scheduled Loops.Benot Dupont de Dinechin
1992MICROStaCS: a Static Control Superscalar architecture.Benot Dupont de Dinechin
1991SCA ultra fast Euclidean division algorithm for prime memory systems.Benot Dupont de Dinechin