| 2025 | ACSSC | Optimizing Internal Data Width in FFT Accelerators for Signal-to-Noise Ratio and Area Efficiency. | Daniel A. Chevy, Bevan M. Baas |
| 2025 | ACSSC | High-Throughput and Small-Area Huffman Decoder for Baseline JPEG Using Small Memory Arrays. | Yechengnuo Zhang, Derek Li, Bevan M. Baas |
| 2021 | ASPDAC | Canonical Huffman Decoder on Fine-grain Many-core Processor Arrays. | Satyabrata Sarangi, Bevan M. Baas |
| 2021 | ISCAS | DeepScaleTool: A Tool for the Accurate Estimation of Technology Scaling in the Deep-Submicron Era. | Satyabrata Sarangi, Bevan M. Baas |
| 2018 | ACSSC | Display Stream Compression Encoder Architectures for Real-time 4K and 8K Video Encoding. | Shifu Wu, Snehlata Gutgutia, Massimo Alioto, Bevan M. Baas |
| 2015 | ACSSC | A software LDPC decoder implemented on a many-core array of programmable processors. | Brent Bohnenstiehl, Bevan M. Baas |
| 2015 | ACSSC | Area efficient backprojection computation with reduced floating-point word width for SAR image formation. | Jon J. Pimentel, Aaron Stillmaker, Brent Bohnenstiehl, Bevan M. Baas |
| 2014 | ACSSC | Scalable hardware-based power management for many-core systems. | Bin Liu, Brent Bohnenstiehl, Bevan M. Baas |
| 2014 | ACSSC | Hybrid floating-point modules with low area overhead on a fine-grained processing core. | Jon J. Pimentel, Bevan M. Baas |
| 2012 | ICPADS | Fine-Grained Energy-Efficient Sorting on a Many-Core Processor Array. | Aaron Stillmaker, Lucas Stillmaker, Bevan M. Baas |
| 2011 | ACSSC | A high-performance area-efficient AES cipher on a many-core platform. | Bin Liu, Bevan M. Baas |
| 2011 | ACSSC | A reduced routing network architecture for partial parallel LDPC decoders. | Houshmand Shirani-mehr, Tinoosh Mohsenin, Bevan M. Baas |
| 2011 | ACSSC | A fine-grained parallel implementation of a H.264/AVC encoder on a 167-processor computational platform. | Zhibin Xiao, Stephen Le, Bevan M. Baas |
| 2011 | ICCD | RoShaQ: High-performance on-chip router with shared queues. | Anh Thien Tran, Bevan M. Baas |
| 2011 | ISCAS | Low power LDPC decoder with efficient stopping scheme for undecodable blocks. | Tinoosh Mohsenin, Houshmand Shirani-mehr, Bevan M. Baas |
| 2010 | DAC | Circuit modeling for practical many-core architecture design exploration. | Dean Truong, Bevan M. Baas |
| 2009 | ISCAS | The Design of a Reconfigurable Continuous-flow Mixed-radix FFT Processor. | Anthony T. Jacobson, Dean Nguyen Truong, Bevan M. Baas |
| 2009 | ISCAS | Multi-Split-Row Threshold Decoding Implementations for LDPC Codes. | Tinoosh Mohsenin, Dean Nguyen Truong, Bevan M. Baas |
| 2009 | ISCAS | A Low-cost High-speed Source-synchronous Interconnection Technique for GALS Chip Multiprocessors. | Anh Thien Tran, Dean Nguyen Truong, Bevan M. Baas |
| 2008 | ACSSC | A thresholding algorithm for improved Split-Row decoding of LDPC codes. | Tinoosh Mohsenin, Pascal Urard, Bevan M. Baas |
| 2008 | ACSSC | A complete real-time 802.11a baseband receiver implemented on an array of programmable processors. | Anh Thien Tran, Dean Nguyen Truong, Bevan M. Baas |
| 2008 | ICCD | A high-performance parallel CAVLC encoder on a fine-grained many-core system. | Zhibin Xiao, Bevan M. Baas |
| 2008 | ISCAS | Dynamic voltage and frequency scaling circuits with two supply voltages. | Wayne H. Cheng, Bevan M. Baas |
| 2008 | ISCAS | A low-area interconnect architecture for chip multiprocessors. | Zhiyi Yu, Bevan M. Baas |
| 2007 | ICASSP | High-Throughput LDPC Decoders Using A Multiple Split-Row Method. | Tinoosh Mohsenin, Bevan M. Baas |
| 2006 | ICCD | Split-Row: A Reduced Complexity, High Throughput LDPC Decoder Architecture. | Tinoosh Mohsenin, Bevan M. Baas |
| 2006 | ICCD | Implementing Tile-based Chip Multiprocessors with GALS Clocking Styles. | Zhiyi Yu, Bevan M. Baas |
| 2005 | ICASSP | A generalized cached-FFT algorithm. | Bevan M. Baas |