Biju K. Raveendran
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
6
Venues
5
Active years
2006–2021
Best venue rank
National
Where they publish
Papers
6 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2021 | HPCC | pmcEDF: An Energy Efficient Procrastination Scheduler for Multi-core Mixed Criticality Systems. | Louella Colaco, Amol Pai, Biju K. Raveendran, Sasikumar Punnekkat |
| 2017 | VLSID | DTLB: Deterministic TLB for Tightly Bound Hard Real-Time Systems. | Kajal Varma, Geeta Patil, Biju K. Raveendran |
| 2016 | CoDIT | DPS: A dynamic procrastination scheduler for multi-core/multi-processor hard real time systems. | Shubhangi K. Gawali, Biju K. Raveendran |
| 2015 | VLSID | Way Halted Prediction Cache: An Energy Efficient Cache Architecture for Embedded Processors. | Neethu Bal Mallya, Geeta Patil, Biju K. Raveendran |
| 2008 | SAC | Evaluation of priority based real time scheduling algorithms: choices and tradeoffs. | Biju K. Raveendran, Sundar Balasubramaniam, S. Gurunarayanan |
| 2006 | ICDCN | Variants of Priority Scheduling Algorithms for Reducing Context-Switches in Real-Time Systems. | Biju K. Raveendran, K. Durga Prasad, Sundar Balasubramaniam, S. Gurunarayanan |