Brian Cline
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
18
Venues
5
Active years
2006–2021
Best venue rank
A*
Where they publish
Papers
18 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2021 | ISLPED | Power Delivery and Thermal-Aware Arm-Based Multi-Tier 3D Architecture. | Lingjun Zhu, Tuan Ta, Rossana Liu, Rahul Mathur, Xiaoqing Xu, Shidhartha Das, Ankit Kaul, Alejandro Rico, Doug Joseph, Brian Cline, Sung Kyu Lim |
| 2019 | ISLPED | Enhanced 3D Implementation of an Arm | Xiaoqing Xu, Mudit Bhargava, Steve Moore, Saurabh Sinha, Brian Cline |
| 2018 | DAC | Accurate processor-level wirelength distribution model for technology pathfinding using a modernized interpretation of rent's rule. | Divya Prasad, Saurabh Sinha, Brian Cline, Steve Moore, Azad Naeemi |
| 2017 | ICCAD | Standard cell library design and optimization methodology for ASAP7 PDK: (Invited paper). | Xiaoqing Xu, Nishi Shah, Andrew Evans, Saurabh Sinha, Brian Cline, Greg Yeric |
| 2017 | ICCD | DTCO for DSA-MP Hybrid Lithography with Double-BCP Materials in Sub-7nm Node. | Jiaojiao Ou, Xiaoqing Xu, Brian Cline, Greg Yeric, David Z. Pan |
| 2017 | ISLPED | Frequency and time domain analysis of power delivery network for monolithic 3D ICs. | Kyungwook Chang, Shidhartha Das, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim |
| 2016 | DAC | Match-making for monolithic 3D IC: finding the right technology node. | Kyungwook Chang, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim |
| 2016 | DAC | Near-threshold computing in FinFET technologies: opportunities for improved voltage scalability. | Nathaniel Ross Pinckney, Lucian Shifren, Brian Cline, Saurabh Sinha, Supreet Jeloka, Ronald G. Dreslinski, Trevor N. Mudge, Dennis Sylvester, David T. Blaauw |
| 2016 | ICCAD | Cascade2D: A design-aware partitioning approach to monolithic 3D IC with 2D commercial tools. | Kyungwook Chang, Saurabh Sinha, Brian Cline, Raney Southerland, Michael Doherty, Greg Yeric, Sung Kyu Lim |
| 2016 | ISLPED | Four-tier Monolithic 3D ICs: Tier Partitioning Methodology and Power Benefit Study. | Kwang Min Kim, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim |
| 2015 | ISLPED | Power benefit study of monolithic 3D IC at the 7nm technology node. | Kyungwook Chang, Kartik Acharya, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim |
| 2014 | ICCD | DFM is dead - Long live DFM. | Robert C. Aitken, David Pietromonaco, Brian Cline |
| 2012 | DAC | Exploring sub-20nm FinFET design with predictive technology models. | Saurabh Sinha, Greg Yeric, Vikas Chandra, Brian Cline, Yu Cao |
| 2012 | ISLPED | Design benchmarking to 7nm with FinFET predictive technology models. | Saurabh Sinha, Brian Cline, Greg Yeric, Vikas Chandra, Yu Cao |
| 2008 | DAC | Leakage power reduction using stress-enhanced layouts. | Vivek Joshi, Brian Cline, Dennis Sylvester, David T. Blaauw, Kanak Agarwal |
| 2008 | DATE | Transistor-Specific Delay Modeling for SSTA. | Brian Cline, Kaviraj Chopra, David T. Blaauw, Andres Torres, Savithri Sundareswaran |
| 2008 | ICCAD | STEEL: a technique for stress-enhanced standard cell library design. | Brian Cline, Vivek Joshi, Dennis Sylvester, David T. Blaauw |
| 2006 | ICCAD | Analysis and modeling of CD variation for statistical static timing. | Brian Cline, Kaviraj Chopra, David T. Blaauw, Yu Cao |