Cangyuan Li
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
8
Venues
6
Active years
2021–2026
Best venue rank
A*
Where they publish
Papers
8 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2026 | ACL | ChipSeek: Optimizing Verilog Generation via EDA-Integrated Reinforcement Learning. | Zhirong Chen, Kaiyan Chang, Zhuolin Li, Cangyuan Li, Xinyang He, Chujie Chen, Mengdi Wang, Haobo Xu, Yinhe Han, Huawei Li, Ying Wang |
| 2026 | DATE | FHEx: Transforming Generic Compute Chips into Secure FHE Engines via a Hardware-software Co-designed Framework. | Yibo Du, Ying Wang, Mengdi Wang, Cangyuan Li, Lian Liu, Hui Li, Kai Zhang, Yinhe Han |
| 2026 | ISCA | AutoFHE: An Automatic Hardware Generation Framework for Domain-Specific FHE Accelerators. | Yibo Du, Cangyuan Li, Bing Li, Mengdi Wang, Lian Liu, Shixin Zhao, Yinhe Han, Ying Wang |
| 2026 | ISCA | Unlocking Pipeline Parallelism for Bootstrapping: A Pipelined Multi-Chiplet TFHE Accelerator. | Yibo Du, Mengdi Wang, Cangyuan Li, Yinhe Han, Ying Wang |
| 2024 | DAC | Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework. | Kaiyan Chang, Kun Wang, Nan Yang, Ying Wang, Dantong Jin, Wenlong Zhu, Zhirong Chen, Cangyuan Li, Hao Yan, Yunhao Zhou, Zhuoliang Zhao, Yuan Cheng, Yudong Pan, Yiqi Liu, Mengdi Wang, Shengwen Liang, Yinhe Han, Huawei Li, Xiaowei Li |
| 2024 | ICCAD | Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation. | Kaiyan Chang, Zhirong Chen, Yunhao Zhou, Wenlong Zhu, Kun Wang, Haobo Xu, Cangyuan Li, Mengdi Wang, Shengwen Liang, Huawei Li, Yinhe Han, Ying Wang |
| 2023 | DAC | APPEND: Rethinking ASIP Synthesis in the Era of AI. | Cangyuan Li, Ying Wang, Huawei Li, Yinhe Han |
| 2021 | USENIX | GLIST: Towards In-Storage Graph Learning. | Cangyuan Li, Ying Wang, Cheng Liu, Shengwen Liang, Huawei Li, Xiaowei Li |