| 2009 | DATE | Solver technology for system-level to RTL equivalence checking. | Alfred Klbl, Reily Jacoby, Himanshu Jain, Carl Pixley |
| 2007 | DAC | Memory Modeling in ESL-RTL Equivalence Checking. | Alfred Klbl, Jerry R. Burch, Carl Pixley |
| 2007 | DATE | A compositional approach to the combination of combinational and sequential equivalence checking of circuits without known reset states. | In-Ho Moon, Per Bjesse, Carl Pixley |
| 2004 | FMCAD | Non-miter-based Combinational Equivalence Checking by Comparing BDDs with Different Variable Orders. | In-Ho Moon, Carl Pixley |
| 2004 | MEMOCODE | Designers want proofs - but show me the money. | Carl Pixley, D. Meyers, S. McMaster, A. Chittor |
| 2003 | DAC | Formal verification - prove it or pitch it. | Rajesh K. Gupta, Shishpal Rawat, Sandeep K. Shukla, Brian Bailey, Daniel K. Beece, Masahiro Fujita, Carl Pixley, John O'Leary, Fabio Somenzi |
| 2003 | DAC | Constraint synthesis for environment modeling in functional verification. | Jun Yuan, Ken Albin, Adnan Aziz, Carl Pixley |
| 2003 | ICCAD | A Framework for Constrained Functional Verification. | Jun Yuan, Carl Pixley, Adnan Aziz, Ken Albin |
| 2002 | FMCAD | Simplifying Circuits for Formal Verification Using Parametric Representation. | In-Ho Moon, Hee-Hwan Kwak, James H. Kukula, Thomas R. Shiple, Carl Pixley |
| 2002 | ICCAD | Simplifying Boolean constraint solving for random simulation-vector generation. | Jun Yuan, Ken Albin, Adnan Aziz, Carl Pixley |
| 1999 | ICCAD | Modeling design constraints and biasing in simulation using BDDs. | Jun Yuan, Kurt Shultz, Carl Pixley, Hillel Miller, Adnan Aziz |
| 1999 | PDPTA | Integrated Formal and Informal Design Verification of Commercial Integrated Circuits. | Carl Pixley, Kurt Shultz, Jun Yuan |
| 1998 | CAV | Design Constraints in Symbolic Model Checking. | Matt Kaufmann, Andrew Martin, Carl Pixley |
| 1998 | ICCAD | Approximate reachability don't cares for CTL model checking. | In-Ho Moon, Jae-Young Jang, Gary D. Hachtel, Fabio Somenzi, Jun Yuan, Carl Pixley |
| 1997 | DAC | Formal Verification of FIRE: A Case Study. | Jae-Young Jang, Shaz Qadeer, Matt Kaufmann, Carl Pixley |
| 1997 | ICCD | Intertwined Development and Formal Verification of a 60x Bus Model. | Matt Kaufmann, Carl Pixley |
| 1996 | ITC | Commercial Design Verification: Methodology and Tools. | Carl Pixley, Noel R. Strader, William C. Bruce, Jaehong Park, Matt Kaufmann, Kurt Shultz, Michael Burns, Jainendra Kumar, Jun Yuan, Janet Nguyen |
| 1995 | DAC | The Validity of Retiming Sequential Circuits. | Vigyan Singhal, Carl Pixley, Richard L. Rudell, Robert K. Brayton |
| 1995 | ISCAS | Power-Up Delay for Retiming Digital Circuits. | Vigyan Singhal, Robert K. Brayton, Carl Pixley |
| 1994 | CAV | The Verifiacation Problem for Safe Replaceability. | Vigyan Singhal, Carl Pixley |
| 1994 | ICCAD | Multi-level synthesis for safe replaceability. | Carl Pixley, Vigyan Singhal, Adnan Aziz, Robert K. Brayton |
| 1993 | DAC | Minimum Length Synchronizing Sequences of Finite State Machine. | June-Kyung Rho, Fabio Somenzi, Carl Pixley |
| 1992 | DAC | Exact Calculation of Synchronization Sequences Based on Binary Decision Diagrams. | Carl Pixley, Seh-Woong Jeong, Gary D. Hachtel |
| 1991 | ICCAD | Calculating Resetability and Reset Sequences. | Carl Pixley, Gary Beihl |
| 1991 | ICCD | Automatic Derivation of FSM Specification to Implementation Encoding. | Carl Pixley, Gary Beihl, Ernesto Pacas-Skewes |
| 1990 | CAV | Introduction to a Computational Theory and Implementation of Sequential Hardware Equivalence. | Carl Pixley |