Chaitanya Sathe
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
2
Venues
2
Active years
2007–2009
Best venue rank
B
Where they publish
Papers
2 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2009 | ASPDAC | Automated design and optimization of circuits in emerging technologies. | Rajesh Amratlal Thakker, Chaitanya Sathe, Angada B. Sachid, Maryam Shojaei Baghini, V. Ramgopal Rao, Mahesh B. Patil |
| 2007 | VLSID | Modeling and Analysis of Noise Margin in SET Logic. | Chaitanya Sathe, Santanu Mahapatra |