Chan-Wei Huang
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
1
Venues
1
Active years
2006–2006
Best venue rank
C
Where they publish
Papers
1 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2006 | ISCAS | Self-sampled vernier delay line for built-in clock jitter measurement. | Kuo-Hsing Cheng, Chan-Wei Huang, Shu-Yu Jiang |