| 2021 | ISCA | RingCNN: Exploiting Algebraically-Sparse Ring Tensors for Energy-Efficient CNN-Based Computational Imaging. | Chao-Tsung Huang |
| 2020 | ICASSP | Ernet Family: Hardware-Oriented Cnn Models For Computational Imaging Using Block-Based Inference. | Chao-Tsung Huang |
| 2020 | ICASSP | FIR Filter Design and Implementation for Phase-Based Processing. | Shih-Yao Huang, Wei-Chih Chen, Chao-Tsung Huang |
| 2020 | ICASSP | Fast and Accurate Embedded DCNN for Rgb-D Based Sign Language Recognition. | Ching-Chen Wang, Ching-Te Chiu, Chao-Tsung Huang, Yu-Chun Ding, Li-Wei Wang |
| 2019 | ICASSP | System and VLSI Implementation of Phase-based View Synthesis. | Han-Chih Huang, Yu-Chih Wang, Wei-Chih Chen, Ping-Yen Lin, Chao-Tsung Huang |
| 2019 | MICRO | eCNN: A Block-Based and Highly-Parallel CNN Accelerator for Edge Inference. | Chao-Tsung Huang, Yu-Chun Ding, Huan-Ching Wang, Chi-Wen Weng, Kai-Ping Lin, Li-Wei Wang, Li-De Chen |
| 2018 | ICASSP | A 320M Pixel/S Vlsi Architecture Design of Weighted Mode Filter for 4K Ultra-Hd Depth Upsampling. | Bo-Hsiang Yang, Li-De Chen, Chao-Tsung Huang |
| 2017 | ICCV | Robust Pseudo Random Fields for Light-Field Stereo Matching. | Chao-Tsung Huang |
| 2016 | ISCAS | VLSI architecture design of weighted mode filter for Full-HD depth map upsampling at 30fps. | Li-De Chen, Yu-Ling Hsiao, Chao-Tsung Huang |
| 2016 | ISCAS | Fast realistic block-based refocusing for sparse light fields. | Li-Ren Huang, Yu-Wen Wang, Chao-Tsung Huang |
| 2015 | CVPR | Bayesian inference for neighborhood filters with application in denoising. | Chao-Tsung Huang |
| 2015 | ICASSP | Fast realistic refocusing for sparse light fields. | Chao-Tsung Huang, Jui Chin, Hong-Hui Chen, Yu-Wen Wang, Liang-Gee Chen |
| 2014 | ICIP | Energy and area-efficient hardware implementation of HEVC inverse transform and dequantization. | Mehul Tikekar, Chao-Tsung Huang, Vivienne Sze, Anantha P. Chandrakasan |
| 2013 | VCIP | HEVC interpolation filter architecture for quad full HD decoding. | Chao-Tsung Huang, Chiraag Juvekar, Mehul Tikekar, Anantha P. Chandrakasan |
| 2006 | ICASSP | Line Buffer Wordlength Analysis for Line-Based 2-D DWT. | Chih-Chi Cheng, Chao-Tsung Huang, Jing-Ying Chang, Liang-Gee Chen |
| 2005 | ICASSP | Memory analysis of VLSI architecture for 5/3 and 1/3 motion-compensated temporal filtering [video coding applications]. | Chao-Tsung Huang, Ching-Yeh Chen, Yi-Hau Chen, Liang-Gee Chen |
| 2005 | ICIP | System analysis of VLSI architecture for motion-compensated temporal filtering. | Ching-Yeh Chen, Chao-Tsung Huang, Yi-Hau Chen, Chung-Jr Lian, Liang-Gee Chen |
| 2005 | ISCAS | Multiple-lifting scheme: memory-efficient VLSI implementation for line-based 2-D DWT. | Chih-Chi Cheng, Chao-Tsung Huang, Po-Chih Tseng, Chia-Ho Pan, Liang-Gee Chen |
| 2005 | ISCAS | Single reference frame multiple current macroblocks scheme for multi-frame motion estimation in H.264/AVC. | Tung-Chien Chen, Yu-Wen Huang, Chuan-Yung Tsai, Chao-Tsung Huang, Liang-Gee Chen |
| 2004 | ICASSP | Memory analysis and architecture for two-dimensional discrete wavelet transform. | Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen |
| 2004 | ISCAS | B-spline factorization-based architecture for inverse discrete wavelet transform. | Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen |
| 2004 | ISCAS | Reconfigurable discrete cosine transform processor for object-based video signal processing. | Po-Chih Tseng, Chao-Tsung Huang, Liang-Gee Chen |
| 2003 | ICIP | Hardware implementation of shape-adaptive discrete wavelet transform with the JPEG2000 defaulted (9, 7) filter bank. | Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen |
| 2002 | ISCAS | Efficient VLSI architectures of lifting-based discrete wavelet transform by systematic design method. | Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen |
| 2002 | VCIP | VLSI implementation of shape-adaptive discrete wavelet transform. | Po-Chih Tseng, Chao-Tsung Huang, Liang-Gee Chen |