Che-Lun Hsu
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
3
Venues
3
Active years
2010–2018
Best venue rank
A*
Where they publish
Papers
3 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2018 | ASPDAC | Layout-dependent aging mitigation for critical path timing. | Che-Lun Hsu, Shaofeng Guo, Yibo Lin, Xiaoqing Xu, Meng Li, Runsheng Wang, Ru Huang, David Z. Pan |
| 2015 | DAC | PARR: pin access planning and regular routing for self-aligned double patterning. | Xiaoqing Xu, Bei Yu, Jhih-Rong Gao, Che-Lun Hsu, David Z. Pan |
| 2010 | ISCAS | ESD protection circuit for high-voltage CMOS ICs with improved immunity against transient-induced latchup. | Ming-Dou Ker, Che-Lun Hsu, Wen-Yi Chen |