Chen Kang Lo
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
3
Venues
2
Active years
2009–2011
Best venue rank
B
Where they publish
Papers
3 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2011 | DATE | Cycle-count-accurate processor modeling for fast and accurate system-level simulation. | Chen Kang Lo, Li-Chun Chen, Meng-Huan Wu, Ren-Song Tsay |
| 2010 | ASPDAC | Source-level timing annotation for fast and accurate TLM computation model generation. | Kai-Li Lin, Chen Kang Lo, Ren-Song Tsay |
| 2009 | ASPDAC | Automatic generation of Cycle Accurate and Cycle Count Accurate transaction level bus models from a formal model. | Chen Kang Lo, Ren-Song Tsay |