Cheng-Hsien Chuang
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
1
Venues
1
Active years
2002–2002
Best venue rank
National
Where they publish
Papers
1 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2002 | PDPTA | A Parallel Prefix Circuit with Minimum Layout Cost. | Yen-Chun Lin, Cheng-Hsien Chuang |