| 2025 | ICLR | Optimal Brain Apoptosis. | Mingyuan Sun, Zheng Fang, Jiaxu Wang, Junjie Jiang, Delei Kong, Chenming Hu, Yuetong Fang, Renjing Xu |
| 2017 | ISLPED | Full chip power benefits with negative capacitance FETs. | Sandeep Kumar Samal, Sourabh Khandelwal, Asif Islam Khan, Sayeef S. Salahuddin, Chenming Hu, Sung Kyu Lim |
| 2017 | VLSID | Modeling of Body-Bias Dependence of Overlap Capacitances in Bulk MOSFETs. | Avirup Dasgupta, Chetan Gupta, Anupam Dutta, Yen-Kai Lin, Srikanth Srihari, Ethirajan Tamilmani, Chenming Hu, Yogesh Singh Chauhan |
| 2011 | DAC | New sub-20nm transistors: why and how. | Chenming Hu |
| 2002 | VLSID | Efficient Generation of Delay Change Curves for Noise-Aware Static Timing Analysis. | Kanak Agarwal, Yu Cao, Takashi Sato, Dennis Sylvester, Chenming Hu |
| 2000 | ICCAD | Effects of Global Interconnect Optimizations on Performance Estimation of Deep Submicron Design. | Yu Cao, Chenming Hu, Xuejue Huang, Andrew B. Kahng, Sudhakar Muddu, Dirk Stroobandt, Dennis Sylvester |
| 2000 | ICCAD | Impact of Systematic Spatial Intra-Chip Gate Length Variability on Performance of High-Speed Digital Circuits. | Michael Orshansky, Linda Milor, Pinhong Chen, Kurt Keutzer, Chenming Hu |
| 1999 | DAC | On Thermal Effects in Deep Sub-Micron VLSI Interconnects. | Kaustav Banerjee, Amit Mehrotra, Alberto L. Sangiovanni-Vincentelli, Chenming Hu |
| 1998 | DAC | A Statistical Performance Simulation Methodology for VLSI Circuits. | Michael Orshansky, James C. Chen, Chenming Hu |
| 1997 | ISLPED | Device and technology optimizations for low power design in deep sub-micron regime. | Kai Chen, Chenming Hu |
| 1996 | ISLPED | Device design for low power electronics with accurate deep submicrometer LDD-MOSFET models. | Kai Chen, Yuhua Cheng, Chenming Hu |
| 1989 | ICCD | Reliability issues of MOS and bipolar ICs. | Chenming Hu |